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56f8300 16-bit hybrid controllers freescale.com 56f8323/56F8123 data sheet preliminary technical data mc56f8323 rev. 11.0 10/2004
56f8323 technical data, rev. 11.0 2 freescale semiconductor preliminary document revision history version history description of change rev 1.0 pre-release version, alpha customers only rev 2.0 initial public release rev 3.0 corrected typo in table 10-4 , flash endurance is 10,000 cycles. addressed additional grammar issues. rev 4.0 added package pins to gpio table in section 8. removed reference to pin group 9 in table 10-5 . replacing tbd typical min with values in table 10-17 . editing grammar, spelling, consistency of language throughout family. updated values in regulator parameters, table 10-9 , external clock operation timing requirements table 10-13 , spi timing, table 10-18 , adc parameters, table 10-24 , and io loading coefficients at 10mhz, table 10-25 . rev 5.0 updated values in power-on reset low voltage, table 10-6 . rev 6.0 correcting package pin numbers in table 2-2 , phasea0 changed from 38 to 52, phaseb0 changed from 37 to 51, index0 changed from 36 to 50, and home0 changed from 35 to 49. all pin changes in table 2-2 were do to data entry errors - this package pin-out has not changed rev 7.0 added part 4.8 , added addition text to part 6.9 on por reset, added the word access to fm error interrupt in table 4-3 , removed min and max numbers; only documenting typ. numbers for lvi in table 10-6 . rev 8.0 updated numbers in table 10-7 and table 10-8 with more recent data. corrected typo in table 10-3 in pd characteristics. rev 9.0 replace any reference to flash interface unit with flash memory module; changed example in part 2.2 ; added note on v refh and v reflo in table 2-2 and table 11-1 ; added note to vcap pin in table 2-2 ; corrected typo fival1 and fivah1 in table 4-12 ; removed unneccessary notes in table 10-12 ; corrected temperature range in table 10-14 ; added adc calibration information to table 10-24 and new graphs in figure 10-21 . rev 10.0 clarification to table 10-23 , corrected digital input current low (pull-up enabled) numbers in table 10-5 . removed text and table 10-2; replaced with note to table 10-1 . rev. 11.0 added 56F8123 information; edited to indicate differences in 56f8323 and 56F8123.reformatted for freescale look and feel. updated temperature sensor and adc tables, then updated balance of electrical tables for consistency throughout the family. clarified i/o power description in table 2-2 , added note to table 10-7 and clarified section 12.3 . please see http://www.freescale.com/semiconductors for the most current data sheet revision.
56f8323 technical data, rev. 11.0 freescale semiconductor 3 preliminary 56f8323/56F8123 block diagram program controller and hardware looping unit data alu 16 x 16 + 36 ?> 36-bit mac three 16-bit input registers four 36-bit accumulators address generation unit bit manipulation unit 16-bit 56800e core interrupt controller cop/ watchdog 4 irqa pdb pdb xab1 xab2 xdb2 cdbr spi0 or sci1 or gpiob ipbus bridge (ipbb) decoding peripherals peripheral device selects rw control ipab ipwdb iprdb system bus control r/w control pab pab cdbw cdbr cdbw jtag/ eonce port digital reg analog reg low voltage supervisor v dd v ss v dda v ssa 5 44 2 reset 3 6 quad timer c or sci0 or gpioc 5 quadrature de cod e r 0 o r quad timer a or gpio b flexcan or gpioc 2 4 vref pll clock generator* integration module system p o r o s c clock resets pwm outputs current sense inputs pwma or spi1 or gpioa temp_sense *includes on-chip relaxation oscillator 3 fault input s ocr_dis v cap 4 3 ad0 4 ad1 4 xtal or gpioc extal or gpioc data memory 4k x 16 flash 4k x 16 ram memory program memory 16k x 16 flash 2k x 16 ram 4k x 16 boot flash 56f8323/56F8123 general description note: features in italics are not available in the 56F8123 device. ? up to 60 mips at 60mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? 32kb program flash ? 4kb program ram ? 8kb data flash ? 8kb data ram ?8kb boot flash ? one 6-channel pwm module ? two 4-channel 12-bit adcs ? temperature sensor ? one quadrature decoder ? one flexcan module ? up to two serial communication interfaces (scis) ? up to two serial peripheral interfaces (spis) ? two general-purpose quad timers ? computer operating properly (cop)/watchdog ? on-chip relaxation oscillator ? jtag/enhanced on-chip emulation (once?) for unobtrusive, real-time debugging ?up to 27 gpio lines ? 64-pin lqfp package
56f8323 technical data, rev. 11.0 4 freescale semiconductor preliminary part 1: overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 56f8323/56F8123 features . . . . . . . . . . . . . 5 1.2. device description . . . . . . . . . . . . . . . . . . . . 7 1.3. award-winning development environment . 8 1.4. architecture block diagram . . . . . . . . . . . . . 9 1.5. product documentation . . . . . . . . . . . . . . . 13 1.6. data sheet conventions . . . . . . . . . . . . . . 13 part 2: signal/connection descriptions . . . 14 2.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2. signal pins . . . . . . . . . . . . . . . . . . . . . . . . . 17 part 3: on-chip clock synthesis (occs) . . 28 3.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2. external clock operation . . . . . . . . . . . . . . 28 3.3. use of on-chip relaxation oscillator . . . . . 29 3.4. internal clock operation . . . . . . . . . . . . . . . 30 3.5. registers . . . . . . . . . . . . . . . . . . . . . . . . . . 31 part 4: memory map . . . . . . . . . . . . . . . . . . . 31 4.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2. program map . . . . . . . . . . . . . . . . . . . . . . . 31 4.3. interrupt vector table . . . . . . . . . . . . . . . . . 32 4.4. data map . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.5. flash memory map . . . . . . . . . . . . . . . . . . . 35 4.6. eonce memory map . . . . . . . . . . . . . . . . . 37 4.7. peripheral memory mapped registers . . . . 38 4.8. factory programmed memory . . . . . . . . . . 55 part 5: interrupt controller (itcn) . . . . . . . . 55 5.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3. functional description . . . . . . . . . . . . . . . . 56 5.4. block diagram . . . . . . . . . . . . . . . . . . . . . . 58 5.5. operating modes . . . . . . . . . . . . . . . . . . . . 58 5.6. register descriptions . . . . . . . . . . . . . . . . . 59 5.7. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 part 6: system integration module (sim) . . 82 6.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3. operating modes . . . . . . . . . . . . . . . . . . . . 83 6.4. operating mode register . . . . . . . . . . . . . . 83 6.5. register descriptions . . . . . . . . . . . . . . . . . 84 6.6. clock generation overview . . . . . . . . . . . . 96 6.7. power-down modes . . . . . . . . . . . . . . . . . . 96 6.8. stop and wait mode disable function . . . . 97 6.9. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 part 7: security features . . . . . . . . . . . . . . . 98 7.1. operation with security enabled . . . . . . . . 98 7.2. flash access blocking mechanisms . . . . . 98 part 8: general purpose input/output (gpio) . . . . . . . . . . . . . . . . . . . . . . . 101 8.1. introduction . . . . . . . . . . . . . . . . . . . . . . . . 101 8.2. configuration . . . . . . . . . . . . . . . . . . . . . . . 101 8.3. memory maps . . . . . . . . . . . . . . . . . . . . . . 103 part 9: joint test action group (jtag) . 103 9.1. jtag information . . . . . . . . . . . . . . . . . . . .103 part 10: specifications . . . . . . . . . . . . . . . 104 10.1. general characteristics . . . . . . . . . . . . . .104 10.2. dc electrical characteristics . . . . . . . . . . 108 10.3. ac electrical characteristics . . . . . . . . . . 112 10.4. flash memory characteristics . . . . . . . . . 113 10.5. external clock operation timing . . . . . . . 114 10.6. phase locked loop timing . . . . . . . . . . .115 10.7. crystal oscillator parameters . . . . . . . . . 115 10.8. reset, stop, wait, mode select, and interrupt timing . . . . . . . . . . . . . . 117 10.9. serial peripheral interface (spi) timing . . 119 10.10. quad timer timing . . . . . . . . . . . . . . . . 122 10.11. quadrature decoder timing . . . . . . . . . . 122 10.12. serial communication interface (sci) timing . . . . . . . . . . . . . . . . . . . . . 123 10.13. controller area network (can) timing . 124 10.14. jtag timing . . . . . . . . . . . . . . . . . . . . . 124 10.15. analog-to-digital converter (adc) parameters . . . . . . . . . . . . . . . . . 126 10.16. equivalent circuit for adc inputs . . . . . .129 10.17. power consumption . . . . . . . . . . . . . . . . 129 part 11: packaging . . . . . . . . . . . . . . . . . . 131 11.1. 56f8323 package and pin-out information . . . . . . . . . . . . . . . . . . 131 11.2. 56F8123 package and pin-out information . . . . . . . . . . . . . . . . . . 133 part 12: design considerations . . . . . . . . 136 12.1. thermal design considerations . . . . . . . . 136 12.2. electrical design considerations . . . . . . . 137 12.3. power distribution and i/o ring implementation . . . . . . . . . . . . . .138 part 13: ordering information . . . . . . . . . 139 table of contents
56f8323/56F8123 features 56f8323 technical data, rev. 11.0 freescale semiconductor 5 preliminary part 1 overview 1.1 56f8323/56F8123 features 1.1.1 hybrid controller core ? efficient 16-bit 56800e family engine with dual harvard architecture ? up to 60 million instructions per second (mips) at 60mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? arithmetic and logic multi-bit shifter ? parallel instruction set with unique addressing modes ? hardware do and rep loops ? three internal address buses ? four internal data buses ? instruction set supports both dsp and controller functions ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/eonce debug programming interface 1.1.2 differences between devices table 1-1 outlines the key differences between the 56f8323 and 56F8123 devices. table 1-1 device differences feature 56f8323 56F8123 guaranteed speed 60mhz/60 mips 40mhz/40 mips program ram 4kb not available data flash 8kb not available pwm 1 x 6 not available can 1 not available quadrature decoder 1 x 4 not available temperature sensor 1 not available dedicated gpio 10
56f8323 technical data, rev. 11.0 6 freescale semiconductor preliminary 1.1.3 memory note: features in italics are not available in the 56F8123 device. ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? flash security protection ? on-chip memory, including a low-cost, high-volume flash solution 32kb of program flash 4kb of program ram 8kb of data flash 8kb of data ram 8kb of boot flash ? eeprom emulation capability 1.1.4 peripheral circuits note: features in italics are not available in the 56F8123 device. ? one pulse width modulator module with six pwm outputs, three current sense inputs and three fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes ? two 12-bit, analog-to-digital converters (adcs), which support two simultaneous conversions with dual, 4-pin multiplexed inputs; adc and pwm modules can be synchronized through timer c, channel 2 ? temperature sensor can be connected, on the board, to any of the adc inputs to monitor the on-chip temperature ? two 16-bit quad timer modules (tmr) totaling seven pins: in the 56f8323, timer a works in conjunction with quad decoder 0 and timer c works in conjunction with the pwma and adca in the 56F8123, timer c works in conjunction with adca ? one quadature decoder which works in conjunction with quad timer a ? flexcan (can version 2.0 b-compliant) module with 2-pin port for transmit and receive ? up to two serial communication interfaces (scis) ? up to two serial peripheral interfaces (spis) ? computer operating properly (cop)/watchdog timer ? one dedicated external interrupt pin ? 27 general purpose i/o (gpio) pins ? integrated power-on reset and low-voltage interrupt module ? jtag/enhanced on-chip emulation (once?) for unobtrusive, processor speed-independent, real-time debugging ? software-programmable, phase lock loop (pll) ? on-chip relaxation oscillator
device description 56f8323 technical data, rev. 11.0 freescale semiconductor 7 preliminary 1.1.5 energy information ? fabricated in high-density cmos with 5v tolerant, ttl-compatible digital inputs ? on-board 3.3v down to 2.6v voltage regulator for powering internal logic and memories ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available ? adc smart power management ? each peripheral can be individually disabled to save power 1.2 device description the 56f8323 and 56F8123 are members of the 56800e core-based family of hybrid controllers. each combines, on a single chip, the processing power of a digital signal processor (dsp) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of their low cost, configuration flexibility, and compact program code, the 56f8323 and 56F8123 are well-suited for many applications. the devices include many peripherals that are especially useful for automotive control (56f8323 only); industrial control and networking; motion control; home appliances; general purpose inverters; smart sensors; fire and security systems; power management; and medical monitoring applications. the 56800e core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the mcu-style programming model and optimized instruction set allow straightforward generation of efficient, compact dsp and control code. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the 56f8323 and 56F8123 support program execution from internal memories. two data operands can be accessed from the on-chip data ram per instruction cycle. these devices also provide one external dedicated interrupt line and up to 27 general purpose input/output (gpio) lines, depending on peripheral configuration. 1.2.1 56f8323 features the 56f8323 hybrid controller includes 32kb of program flash and 8kb of data flash, each programmable through the jtag port, with 4kb of program ram and 8kb of data ram. a total of 8kb of boot flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main program and data flash memory areas. both program and data flash memories can be independently bulk erased or erased in pages. program flash page erase size is 1kb. boot and data flash page erase size is 512 bytes. the boot flash memory can also be either bulk or page erased. a key application-specific feature of the 56f8323 is the inclusion of one pulse width modulator (pwm) module. this module incorporates three complementary, individually programmable pwm signal output pairs and is also capable of supporting six independent pwm functions to enhance motor control functionality. complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. the up-counter value
56f8323 technical data, rev. 11.0 8 freescale semiconductor preliminary is programmable to support a continuously variable pwm frequency. edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. the device is capable of controlling most motor types: acim (ac induction motors); both bdc and bldc (brush and brushless dc motors); srm and vrm (switched and variable reluctance motors); and stepper motors. the pwm incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. a smoke-inhibit, write-once protection feature for key parameters is also included. a patented pwm waveform distortion correction circuit is also provided. each pwm is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1/2 (center-aligned mode only) to 16. the pwm module provides reference outputs to synchronize the analog-to-digital converters (adcs) through quad timer c, channel 2. the 56f8323 incorporates one quadrature decoder capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. speed computation capabilities accommodate both fast- and slow-moving shafts. an integrated watchdog timer in the quadrature decoder can be programmed with a time-out value to alarm when no shaft motion is detected. each input is filtered to ensure only true transitions are recorded. this hybrid controller also provides a full set of standard programmable peripherals that include two serial communications interfaces (scis), two serial peripheral interfaces (spis), two quad timers, and flexcan. any of these interfaces can be used as general purpose input/outputs (gpios) if that function is not required. a flex controller area network (flexcan) interface (can version 2.0 b-compliant) and an internal interrupt controller are also a part of the 56f8323. 1.2.2 56F8123 features the 56F8123 hybrid controller includes 32kb of program flash, programmable through the jtag port, and 8kb of data ram. a total of 8kb of boot flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main program flash memory area. the program flash memory can be independently bulk erased or erased in pages; program flash page erase size is 1kb. the boot flash memory can also be either bulk or page erased. this hybrid controller also provides a full set of standard programmable peripherals that include two serial communications interfaces (scis), two serial peripheral interfaces (spis), and two quad timers. any of these interfaces can be used as general purpose input/outputs (gpios) if that function is not required. an internal interrupt controller is also a part of the 56F8123. 1.3 award-winning development environment processor expert tm (pe) provides a rapid application design (rad) tool that combines easy-to-use component-based software application creation with an expert knowledge system. the codewarrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms), demonstration board kit and development system cards will support concurrent engineering. together, pe, codewarrior and evms create a complete, scalable tools solution for easy, fast, and efficient development.
architecture block diagram 56f8323 technical data, rev. 11.0 freescale semiconductor 9 preliminary 1.4 architecture block diagram note: features in italics are not available in the 56F8123 device and are shaded in the following figures. the 56f8323/56F8123 architecture is shown in figure 1-1 and figure 1-2 . figure 1-1 illustrates how the 56800e system buses communicate with internal memories and the ipbus bridge. table 1-2 lists the internal buses in the 56800e architecture and provides a brief description of their function. figure 1-2 shows the peripherals and control blocks connected to the ipbus bridge. the figures do not show the on-board regulator and power and ground signals. they also do not show the multiplexing between peripherals or the dedicated gpios. please see part 2 signal/connection descriptions , to see which signals are multiplexed with those of other peripherals. also shown in figure 1-2 are connections between the pwm , timer c and adc blocks. these connections allow the pwm and/or timer c to control the timing of the start of adc conversions. the timer c, channel 2, output can generate periodic start (sync) signals to the adc to start its conversions. in another operating mode, the pwm load interrupt (sync output) signal is routed internally to the timer c, channel 2, input as indicated. the timer can then be used to introduce a controllable delay before generating its output signal. the timer output then triggers the adc. to fully understand this interaction, please see the 56f8300 peripheral user manual for clarification on the operation of all three of these peripherals.
56f8323 technical data, rev. 11.0 10 freescale semiconductor preliminary figure 1-1 system bus interfaces note: flash memories are encapsulated within the flash memory (fm) module. flash control is accomplished by the i/o to the fm over the peripheral bus, while reads and writes are completed between the core and the flash memories. note: the primary data ram port is 32 bits wide. other data ports are 16 bits. 56800e program flash program ram data ram data flash ipbus bridge boot flash flash memory module chip tap controller tap linking module 5 not available on the 56F8123 device. to flash control logic jtag / eonce pdb_m[15:0] pab[20:0] cdbw[31:0] xab1[23:0] xab2[23:0] cdbr_m[31:0] xdb2_m[15:0] ipbus external jtag port
architecture block diagram 56f8323 technical data, rev. 11.0 freescale semiconductor 11 preliminary figure 1-2 peripheral subsystem ipbus timer a spi 0 adca 3 8 spi 1 gpio a 4 interrupt controller to/from ipbus bridge pwm a sci 0 8 system por low-voltage interrupt cop reset cop reset quadrature decoder 0 4 gpio b gpio c flexcan sci 1 4 temp_sense clkgen (osc/pll) (rosc) por & lvi sim 2 ch2i ch2o timer c 2 2 sync output not available on the 56F8123 device.
56f8323 technical data, rev. 11.0 12 freescale semiconductor preliminary table 1-2 bus signal names name function program memory interface pdb_m[15:0] program data bus for instruction word fetches or read operations. cdbw[15:0] primary core data bus used for program memory writes. (only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] program memory address bus. data is returned on pdb_m bus. primary data memory interface bus cdbr_m[31:0] primary core data bus for memory reads. addressed via xab1 bus. cdbw[31:0] primary core data bus for memory writes. addressed via xab1 bus. xab1[23:0] primary data address bus. capable of addressing bytes 1 , words, and long data types. data is written on cdbw and returned on cdbr_m. also used to access memory-mapped i/o. 1. byte accesses can only occur in the bottom half of the memory address space. the msb of the address will be forced to 0. secondary data memory interface xdb2_m[15:0] secondary data bus used for secondary data address bus xab2 in the dual memory reads. xab2[23:0] secondary data address bus used for the second of two simultaneous accesses. capable of addressing only words. data is returned on xdb2_m. peripheral interface bus ipbus [15:0] peripheral bus accesses all on-chip peripherals registers. this bus operates at the same clock rate as the primary data memory and therefore generates no delays when accessing the processor. write data is obtained from cdbw. read data is provided to cdbr_m.
product documentation 56f8323 technical data, rev. 11.0 freescale semiconductor 13 preliminary 1.5 product documentation the documents listed in table 1-3 are required for a complete description and proper design with the 56f8323 and 56F8123 devices. documentation is available from local freescale distributors, freescale semiconductor sales offices, freescale literature distribution centers, or online at http://www.freescale.com/semiconductors . table 1-3 chip documentation 1.6 data sheet conventions this data sheet uses the following conventions: topic description order number dsp56800e reference manual detailed description of the 56800e family architecture, 16-bit hybrid controller core processor, and the instruction set dsp56800erm 56f8300 peripheral user manual detailed description of peripherals of the 56800e family of devices mc56f8300um 56f8300 sci/can bootloader user manual detailed description of the sci/can bootloaders 56f8300 family of devices mc56f83xxblum 56f8323/56F8123 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions (this document) mc56f8323 product brief summary description and block diagram of the device core, memory, peripherals and interfaces mc56f8323pb mc56F8123pb errata details any chip issues that might be present mc56f8323e mc56F8123e overbar this is used to indicate a signal that is active when pulled low. for example, the reset pin is active when low. asserted a high true (active high) signal is high or a low true (active low) signal is low. deasserted a high true (active high) signal is low or a low true (active low) signal is high. examples: signal/symbol logic state signal state voltage 1 1. values for v il , v ol , v ih , and v oh are defined by individual product specifications. pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
56f8323 technical data, rev. 11.0 14 freescale semiconductor preliminary part 2 signal/connection descriptions 2.1 introduction the input and output signals of the 56f8323 and 56F8123 are organized into functional groups, as detailed in table 2-1 and as illustrated in figure 2-1 and figure 2-2. in table 2-2 , each table row describes the signal or signals present on a pin. table 2-1 functional group pin allocations functional group number of pins in package 56f8323 56F8123 power (v dd or v dda )66 power option control 1 1 ground (v ss or v ssa )55 supply capacitors 1 & v pp 2 1. if the on-chip regulator is disabled, the v cap pins serve as 2.5v v dd_core power inputs 2. the v pp input shares the irqa input 44 pll and clock 2 2 interrupt and program control 2 2 pulse width modulator (pwm) ports 3 3. pins in this section can function as spi #1 and gpio 12 serial peripheral interface (spi) port 0 4 4. pins in this section can function as sci #1 and gpio 48 quadrature decoder port 0 5 5. alternately, can function as quad timer a pins or gpio 4 can ports 2 analog-to-digital converter (adc) ports 13 13 timer module port c 6 6. two pins can function as sci #0 and gpio note: see table 1-1 for 56F8123 functional differences. 33 timer module port a 4 jtag/enhanced on-chip emulation (eonce) 5 5 temperature sensse 1 dedicated gpio 10
introduction 56f8323 technical data, rev. 11.0 freescale semiconductor 15 preliminary figure 2-1 56f8323 signals identified by functional group (64-pin lqfp) v dd_io v dda_adc v ssa_adc extal (gpioc0) xtal (gpioc1) other supply ports pll and clock or gpio jtag/ eonce port 4 1 4 v cap 1 - v cap 4 4 1 1 tck tms quadrature decoder 0 or quad timer a or gpio phasea0 (ta0, gpiob7) pwma0-1 (gpioa0-1) ana0 - 7 irqa (v pp ) reset spi0 or sci1 or gpio pwma or spi1 or gpio quad timer c or sci0 or gpio 1 1 2 8 5 1 1 56f8323 1 tdi tdo phaseb0 (ta1, gpiob6) index0 (ta2, gpiob5) home0 (ta3, gpiob4) sclk0 (gpiob3) mosi0 (gpiob2) miso0 (rxd1, gpiob1) ss0 (txd1, gpiob0) faulta0 - 2 (gpioa6-8) can_rx (gpioc2) can_tx (gpioc3) adca flexcan or gpio interrupt/ program control 1 1 1 1 1 1 1 1 1 1 3 1 1 1 v ref temp_sense 1 v ss power ground power ground v dda_osc_pll 1 ocr_dis 1 power trst 1 isa0 - 2 (gpioa9-11) 3 tc0 (txd0, gpioc6) 1 tc1 (rxd0, gpioc5) 1 tc3 (gpioc4) pwma2 (ss1 , gpioa2) 1 pwma3 (miso1, gpioa3) 1 pwma4 (mosi1, gpioa4) 1 pwma5 (sclk1, gpioa5) 1 temperature sensor
56f8323 technical data, rev. 11.0 16 freescale semiconductor preliminary figure 2-2 56F8123 signals identified by functional group (64-pin lqfp) v dd_io v dda_adc v ssa_adc extal (gpioc0) xtal (gpioc1) other supply ports pll and clock or gpio jtag/ eonce port 4 1 4 v cap 1 - v cap 4 4 1 1 tck tms ta0 (gpiob7) gpioa0-1 ana0 - 7 irqa (v pp ) reset spi0 or sci1 or gpio spi1 or gpio quad timer c or sci0 or gpio 1 1 2 8 5 1 1 56F8123 1 tdi tdo ta1 (gpiob6) ta2 (gpiob5) ta3 (gpiob4) sclk0 (gpiob3) mosi0 (gpiob2) miso0 (rxd1, gpiob1) ss0 (txd1, gpiob0) gpioa6-8 gpioc2 gpioc3 adca gpio interrupt/ program control 1 1 1 1 1 1 1 1 1 1 3 1 1 1 v ref v ss power ground power ground v dda_osc_pll 1 ocr_dis 1 power trst 1 gpioa9-11 3 tc0 (txd0, gpioc6) 1 tc1 (rxd0, gpioc5) 1 tc3 (gpioc4) s s1 (gpioa2) 1 miso1 (gpioa3) 1 mosi1 (gpioa4) 1 sclk1 (gpioa5) 1 quad timer a or gpio
signal pins 56f8323 technical data, rev. 11.0 freescale semiconductor 17 preliminary 2.2 signal pins after reset, each pin is configured for its primary function (listed first). in the 56F8123, after reset, each pin must be configured for the desired function. the initialization software will configure each pin for the function listed first for each pin, as shown in table 2-2 . any alternate functionality must be programmed. note: signals in italics are not available in the 56F8123 device. if the state during reset lists more than one state for a pin, the first state is the actual reset state. other states show the reset condition of the alternate function, which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral. for example, the sclk0/gpiob3 pin shows that it is tri-stated during reset. if the gpiob_per is changed to select the gpio function of the pin, it will become an input if no other registers are changed. table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description v dd_io 6supply i/o power this pin supplies 3.3v power to the chip i/o interface and also the processor core throught the on-chip voltage regulator, if it is enabled. v dd_io 20 v dd_io 48 v dd_io 59 v dda_osc_pll 42 supply oscillator and pll power this pin supplies 3.3v power to the osc and to the internal regulator that in turn supplies the phase locked loop. it must be connected to a clean analog power supply. v dda_adc 41 supply adc power this pin supplies 3.3v power to the adc modules. it must be connected to a clean analog power supply. v ss 11 supply ground these pins provide ground for chip logic and i/o drivers. v ss 17 v ss 44 v ss 60 v ssa_adc 39 supply adc analog ground this pin supplies an analog ground to the adc modules.
56f8323 technical data, rev. 11.0 18 freescale semiconductor preliminary v cap 1 57 supply supply v cap 1 - 4 when ocr_dis is tied to v ss (regulator enabled), connect each pin to a 2.2 f or greater bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. when ocr_dis is tied to v dd , (regulator disabled), these pins become v dd_core and should be connected to a regulated 2.5v power supply. note: this bypass is required even if the chip is powered with an external supply. v cap 2 23 v cap 3 5 v cap 4 43 ocr_dis 45 on-chip regulator disable tie this pin to v ss to enable the on-chip regulator tie this pin to v dd to disable the on-chip regulator this pin is intended to be a static dc signal from power-up to shut down. do not try to toggle this pin for power savings during operation. extal (gpioc0) 46 input schmitt input/ output input input external crystal oscillator input this input can be connected to an 8mhz external crystal. if an external clock is used, xtal must be used as the input and extal connected to v ss . the input clock can be selected to provide the clock directly to the core. this input clock can also be selected as the input clock for the on-chip pll. port c gpio this gpio pin can be individually programmed as an input or output pin. after reset, the default state is an extal input with pull-ups disabled. xtal (gpioc1) 47 output schmitt input/ output output input crystal oscillator output this output can be connected to an 8mhz external crystal. if an external clock is used, xtal must be used as the input and extal connected to v ss . the input clock can be selected to provide the clock directly to the core. this input clock can also be selected as the input clock for the on-chip pll. port c gpio this gpio pin can be individually programmed as an input or output pin. after reset, the default state is an xtal input with pull-ups disabled. tck 53 schmitt input input, pulled low internally test clock input this input pin provides a gated clock to synchronize the test logic and shift serial data to the jtag/eonce port. the pin is connected internally to a pull-down resistor. a schmitt trigger input is used for noise immunity. table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8323 technical data, rev. 11.0 freescale semiconductor 19 preliminary tms 54 schmitt input input, pulled high internally test mode select input this input pin is used to sequence the jtag tap controllers state machine. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. tdi 55 schmitt input input, pulled high internally test data input this input pin provides a serial input data stream to the jtag/eonce port. it is sampled on the rising edge of tck and has an on-chip pull-up resistor. tdo 56 output tri-stated test data output this tri-stateable output pin provides a serial output data stream from the jtag/eonce port. it is driven in the shift-ir and shift-dr controller states, and changes on the falling edge of tck. trst 58 schmitt input input, pulled high internally test reset as an input, a low signal on this pin provides a reset signal to the jtag tap controller. to ensure complete hardware reset, trst should be asserted whenever reset is asserted. the only exception occurs in a debugging environment when a hardware device reset is required and the eonce/jtag module must not be reset. in this case, assert reset , but do not assert trst . to deactivate the internal pull-up resistor, set the jtag bit in the sim_pudr register. phasea0 (ta0) (gpiob7) (oscillator_ clock) 52 schmitt input schmitt input/ output schmitt input/ output output input input input output phase a quadrature decoder 0, phasea input ta0 timer a, channel 0 port b gpio this gpio pin can be individually programmed as an input or output pin. clock output - can be used to monitor the internal oscillator clock signal (see part 6.5.7 clko select register, sim_clkosr). in the 56f8323, the default state after reset is phasea0. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
56f8323 technical data, rev. 11.0 20 freescale semiconductor preliminary phaseb0 (ta1) (gpiob6) (sys_clk2) 51 schmitt input schmitt input/ output schmitt input/ output output input input input output phase b quadrature decoder 0, phaseb input ta1 timer a ,channel 1 port b gpio this gpio pin can be individually programmed as an input or output pin. clock output - can be used to monitor the internal sys_clk2 signal (see part 6.5.7 clko select register, sim_clkosr). in the 56f8323, the default state after reset is phaseb0. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. index0 (ta2) (gpiob5) (sys_clk) 50 schmitt input schmitt input/ output schmitt input/ output output input input input output index quadrature decoder 0, index input ta2 timer a, channel 2 port b gpio this gpio pin can be individually programmed as an input or output pin. clock output - can be used to monitor the internal sys_clk signal (see part 6.5.7 clko select register, sim_clkosr). in the 56f8323, the default state after reset is index0. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8323 technical data, rev. 11.0 freescale semiconductor 21 preliminary home0 (ta3) (gpiob4) (prescaler_ clock) 49 schmitt input schmitt input/ output schmitt input/ output output input input input output home quadrature decoder 0, home input ta3 timer a, channel 3 port b gpio this gpio pin can be individually programmed as an input or output pin. clock output - can be used to monitor the internal prescaler_clock signal (see part 6.5.7 clko select register, sim_clkosr). in the 56f8323, the default state after reset is home0. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. sclk0 (gpiob3) 25 schmitt input/ output schmitt input/ output tri-stated input spi 0 serial clock in the master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. a schmitt trigger input is used for noise immunity. port b gpio this gpio pin can be individually programmed as an input or output pin. after reset, the default state is sclk0. mosi0 (gpiob2) 24 schmitt input/ output schmitt input/ output tri-stated input spi 0 master out/slave in this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge the slave device uses to latch the data. port b gpio this gpio pin can be individually programmed as an input or output pin. after reset, the default state is mosi0. table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
56f8323 technical data, rev. 11.0 22 freescale semiconductor preliminary miso0 (rxd1) (gpiob1) 22 schmitt input/ output schmitt input schmitt input/ output input input input spi 0 master in/slave out this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. the slave device places data on the miso line a half-cycle before the clock edge the master device uses to latch the data. receive data sci1 receive data input port b gpio this gpio pin can be individually programmed as an input or output pin. after reset, the default state is miso0. ss0 (txd1) (gpiob0) 21 schmitt input output schmitt input/ output input tri-stated input spi 0 slave select ss0 is used in slave mode to indicate to the spi module that the current transfer is to be received. transmit data sci1 transmit data output port b gpio this gpio pin can be individually programmed as an input or output pin. after reset, the default state is ss0 . pwma0 (gpioa0) 3output schmitt input/ output tri-stated input pwma0 this is one of six pwma output pins. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is pwma0. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. pwma1 (gpioa1) 4output schmitt input/ output tri-stated input pwma1 this is one of six pwma output pins. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is pwma1. in the 56F8123, the default state is not one of the functions offered and must be reconfigured table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8323 technical data, rev. 11.0 freescale semiconductor 23 preliminary pwma2 (ss1 ) (gpioa2) 7output schmitt input schmitt input/ output tri-stated input input pwma2 this is one of six pwma output pins. spi 1 slave select ss1 is used in slave mode to indicate to the spi module that the current transfer is to be received. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is pwma2. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. pwma3 (miso1) (gpioa3) 8output schmitt input/ output schmitt input/ output tri-stated input input pwma3 this is one of six pwma output pins. spi 1 master in/slave out this serial data pin is an input to a master device and an output from a slave device. the miso line of a slave device is placed in the high-impedance state if the slave device is not selected. the slave device places data on the miso line a half-cycle before the clock edge the master device uses to latch the data. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is pwma3. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. pwma4 (mosi1) (gpioa4) 9output schmitt input/ output schmitt input/ output tri-stated tri-stated input pwma4 this is one of six pwma output pins. spi 1 master out/slave in this serial data pin is an output from a master device and an input to a slave device. the master device places data on the mosi line a half-cycle before the clock edge the slave device uses to latch the data. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is pwma4. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
56f8323 technical data, rev. 11.0 24 freescale semiconductor preliminary pwma5 (sclk1) (gpioa5) 10 output schmitt input/ output schmitt input/ output tri-stated input input pwma5 this is one of six pwma output pins. spi 1 serial clock in the master mode, this pin serves as an output, clocking slaved listeners. in slave mode, this pin serves as the data clock input. a schmitt trigger input is used for noise immunity. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is pwma5. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. faulta0 (gpioa6) 13 schmitt input schmitt input/ output input input faulta0 this fault input pin is used for disabling selected pwma outputs in cases where fault conditions originate off-chip. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is faulta0. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. faulta1 (gpioa7) 14 schmitt input schmitt input/ output input input faulta1 this fault input pin is used for disabling selected pwma outputs in cases where fault conditions originate off-chip. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is faulta1. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. faulta2 (gpioa8) 15 schmitt input schmitt input/ output input input faulta2 this fault input pin is used for disabling selected pwma outputs in cases where fault conditions originate off-chip. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is faulta2. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8323 technical data, rev. 11.0 freescale semiconductor 25 preliminary isa0 (gpioa9) 16 schmitt input schmitt input/ output input input isa0 this input current status pin is used for top/bottom pulse width correction in complementary channel operation for pwma. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is isa0. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. isa1 (gpioa10) 18 schmitt input schmitt input/ output input input isa1 this input current status pin is used for top/bottom pulse width correction in complementary channel operation for pwma. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is isa1. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. isa2 (gpioa11) 19 schmitt input schmitt input/ output input input isa2 this input current status pin is used for top/bottom pulse width correction in complementary channel operation for pwma. port a gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is isa2. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. ana0 26 input input ana0 - 3 analog inputs to adca, channel 0 ana1 27 ana2 28 ana3 29 ana4 30 input input ana4 - 7 analog inputs to adca, channel 1 ana5 31 ana6 32 ana7 33 v refh 40 schmitt input input v refh analog reference voltage high table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
56f8323 technical data, rev. 11.0 26 freescale semiconductor preliminary v refp 37 input/ output input/ output v refp , v refmid & v refn internal pins for voltage reference which are brought off-chip so that they can be bypassed. connect to a 0.1 f ceramic low esr capacitor v refmid 36 v refn 35 v reflo 38 schmitt input input v reflo analog reference voltage low. this should normally be connected to a low-noise v ss . temp_sense 34 output output temperature sense diode this signal connects to an on-chip diode that can be connected to one of the adc inputs and used to monitor the temperature of the die. must be bypassed with a 0.01 f capacitor can_rx (gpioc2) 61 schmitt input schmitt input/ output input input flexcan receive data this is the can input. this pin has an internal pull-up resistor. port c gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is can_rx. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. can_tx (gpioc3) 62 output schmitt input/ output tri-stated input flexcan transmit data can output port c gpio this gpio pin can be individually programmed as an input or output pin. in the 56f8323, the default state after reset is can_tx. in the 56F8123, the default state is not one of the functions offered and must be reconfigured. tc0 (txd0) (gpioc6) 1schmitt input/ output input schmitt input/ output input tri-stated input tc0 timer c, channel 0 transmit data sci0 transmit data output port c gpio this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tc0. table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
signal pins 56f8323 technical data, rev. 11.0 freescale semiconductor 27 preliminary tc1 (rxd0) (gpioc5) 64 schmitt input/ output schmitt input schmitt input/ output input input input tc1 timer c, channel 1 receive data sci0 receive data input port c gpio this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tc1. tc3 (gpioc4) 63 schmitt input/ output schmitt input/ output input input tc1 timer c channel 3 port c gpio this gpio pin can be individually programmed as an input or output pin. after reset, the default state is tc3. irqa (v pp ) 12 schmitt input input input n/a external interrupt request a the irqa input is an asynchronous external interrupt request during stop and wait mode operation. during other operating modes, it is a synchronized external interrupt request which indicates an external device is requesting service. it can be programmed to be level-sensitive or negative-edge-triggered v pp this pin is used for flash debugging purposes. reset 2schmitt input input reset this input is a direct hardware reset on the processor. when reset is asserted low, the device is initialized and placed in the reset state. a schmitt trigger input is used for noise immunity. the internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. to ensure complete hardware reset, reset and trst should be asserted together. the only exception occurs in a debugging environment when a hardware device reset is required and the jtag/eonce module must not be reset. in this case, assert reset , but do not assert trst . table 2-2 signal and package information for the 64-pin lqfp signal name pin no. type state during reset signal description
56f8323 technical data, rev. 11.0 28 freescale semiconductor preliminary part 3 on-chip clock synthesis (occs) 3.1 introduction refer to the occs chapter of the 56f8300 peripheral user manual for a full description of the occs. the material contained here identifies the specific features of the occs design. 3.2 external clock operation the system clock can be derived from an external crystal, ceramic resonator, or an external system clock signal. to generate a reference frequency using the internal oscillator, a reference crystal or ceramic resonator must be connected between the extal and xtal pins. 3.2.1 crystal oscillator the internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in table 10-15 . a recommended crystal oscillator circuit is shown in figure 3-1 . follow the crystal suppliers recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. the crystal and associated components should be mounted as near as possible to the extal and xtal pins to minimize output distortion and start-up stabilization time. figure 3-1 connecting to a crystal oscillator note: the occs_cohl bit should be set to 1 when a crystal oscillator is used. the reset condition on the occs_cohl bit is 0. please see the cohl bit in the oscillator control (osctl) register, discussed in the 56f8300 peripheral user manual . 3.2.2 ceramic resonator (default) it is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. a typical ceramic resonator circuit is shown in figure 3-2 . refer to the suppliers recommendations when selecting a ceramic resonator and associated components. the resonator and components should be mounted as near as possible to the extal and xtal pins. sample external crystal parameters: r z = 750 k ? note: if the operating temperature range is limited to below 85 o c (105 o c junction), then r z = 10 meg ? clkmode = 0 extal xtal r z cl1 cl2 crystal frequency = 4 - 8mhz (optimized for 8mhz) extal xtal r z
use of on-chip relaxation oscillator 56f8323 technical data, rev. 11.0 freescale semiconductor 29 preliminary figure 3-2 connecting a ceramic resonator note: the occs_cohl bit must be set to 0 when a crystal resonator is used. the reset condition on the occs_cohl bit is 0. please see the cohl bit in the oscillator control (osctl) register, discussed in the 56f8300 peripheral user manual . 3.2.3 external clock source the recommended method of connecting an external clock is illustrated in figure 3-3 . the external clock source is connected to xtal and the extal pin is grounded. the external clock input must be generated using a relatively low impedance driver, as the xtal pin is actually the output pin of the oscillator (it has a very weak driver). figure 3-3 connecting an external clock signal 3.3 use of on-chip relaxation oscillator an internal relaxtion oscillator can supply the reference frequency when an external frequency source of crystal is not used. during a boot or reset sequence, the relaxation oscillator is enabled by default, and the precs bit in the pllcr word is set to 0. if an external oscillator is connected, the relaxation oscillator can be deselected instead by setting the precs bit in the pllcr to 1. if a changeover between internal and external oscillators is required at start up, internal device circuits compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the resulting master clock to the chip. when changing clocks, the user must ensure that the clock source is not switched until the desired clock is enabled and stable. to compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within + 0.1% of 8mhz by trimming an internal capacitor. bits 0-9 of the extal xtal r z sample external ceramic resonator parameters: r z = 750 k ? extal xtal r z c1 cl1 cl2 c2 resonator frequency = 4 - 8mhz (optimized for 8mhz) 3 terminal 2 terminal clkmode = 0 xtal extal external v ss clock note: when using an external clocking source with this configuration, the clkmode and cohl bits of the osctl register should be set to 1.
56f8323 technical data, rev. 11.0 30 freescale semiconductor preliminary osctl (oscillator control) register allow the user to set in an additional offset (trim) to this preset value to increase or decrease capacitance. upon power-up, the default value of this trim is 512 units. each unit added or deleted changes the output frequency by about 0.1%, allowing incremental adjustment until the desired frequency accuracy is achieved. the internal oscillator is calibrated at the factory to 8mhz and the trim value is stored in the flash information block and loaded to the fmopt1 register at reset. when using the relaxation oscillator, the boot code should read the fmopt1 register and set this value as osctl trim. for further information, see the 56f8300 peripherals user manual . 3.4 internal clock operation at reset, both oscillators will be powered up; however, the relaxation oscillator will be the default clock reference for the pll. software should power down the block not being used and program the pll for the correct frequency. figure 3-4 internal clock operation crystal osc relaxation osc clk_mode xtal extal mux mux precs pllcid pll x (1 to 128) postscaler (1, 2, 4, 8) 2 prescaler ( 1, 2, 4, 8) lock detector loss of reference clock detector mux sys_clk2 source to the sim postscaler clk plldb pllcod lck bus interface & control bus interface fref feedback loss of reference clock interrupt mstr_osc f out f out /2 zsrc
registers 56f8323 technical data, rev. 11.0 freescale semiconductor 31 preliminary 3.5 registers when referring to the register definitions for the occs in the 56f8300 peripheral user manual , use the register definitions with the internal relaxation oscillator, since the 56f8323 and 56F8123 contain this oscillator. part 4 memory map 4.1 introduction the 56f8323 and 56F8123 devices are 16-bit motor-control chips based on the 56800e core. these parts use a harvard-style architecture with two independent memory spaces for data and program. on-chip ram and flash memories are used in both spaces. this section provides memory maps for: ? program address space, including the interrupt vector table ? data address space, including the eonce memory and peripheral memory maps on-chip memory sizes for the device are summarized in table 4-1 . flash memories restrictions are identified in the use restrictions column of table 4-1 . note: data flash and program ram are not available on the 56F8123 device. 4.2 program map the program memory map is located in table 4-2 . the operating mode control bits (ma and mb) in the operating mode register (omr) control the program memory map. because the 56f8323 and 56F8123 do not include emi, the omr ma bit, which is used to decide internal or external boot, will have no effect on the program memory map. omr mb reflects the security status of the program flash. after reset, changing the omr mb bit will have no effect on the program flash. table 4-1 chip memory configurations on-chip memory 56f8323 56F8123 use restrictions program flash 32kb 32kb erase / program via flash interface unit and word writes to cdbw data flash 8kb erase / program via flash interface unit and word writes to cdbw. data flash can be read via either cdbr or xdb2, but not by both simultaneously program ram 4kb none data ram 8kb 8kb none program boot flash 8kb 8kb erase / program via flash interface unit and word writes to cdbw
56f8323 technical data, rev. 11.0 32 freescale semiconductor preliminary note: program ram is not available on the 56F8123 device. 4.3 interrupt vector table table 4-3 provides the devices reset and interrupt priority structure, including on-chip peripherals. the table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. as indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. all level 3 interrupts will be serviced before level 2, and so on. for a selected priority level, the lowest vector number has the highest priority. the location of the vector table is determined by the vector base address (vba). please see part 5.6.11 for the reset value of the vba. in some configurations, the reset address and cop reset address will correspond to vector 0 and 1 of the interrupt vector table. in these instances, the first two locations in the vector table must contain branch or jmp instructions. all other entries must contain jsr instructions. note: pwma, can and quadrature decoder are not available on the 56F8123 device. table 4-2 program memory map at reset begin/end address memory allocation p: $1f ffff p: $03 0000 reserved p: $02 ffff p: $02 f800 on-chip program ram 4kb p: $02 f7ff p: $02 1000 reserved p: $02 0fff p: $02 0000 boot flash 8kb cop reset address = $02 0002 boot location = $02 0000 p: $01 ffff p: $00 4000 reserved p: $00 3fff p: $00 0000 internal program flash 32kb table 4-3 interrupt vector table contents 1 peripheral vector number priority level vector base address + interrupt function reserved for reset overlay 2 reserved for cop reset overlay 2 core 2 3 p:$04 illegal instruction core 3 3 p:$06 sw interrupt 3
interrupt vector table 56f8323 technical data, rev. 11.0 freescale semiconductor 33 preliminary core 4 3 p:$08 hw stack overflow core 5 3 p:$0a misaligned long word access core 6 1-3 p:$0c once step counter core 7 1-3 p:$0e once breakpoint unit 0 reserved core 9 1-3 p:$12 once trace buffer core 10 1-3 p:$14 once transmit register empty core 11 1-3 p:$16 once receive register full reserved core 14 2 p:$1c sw interrupt 2 core 15 1 p:$1e sw interrupt 1 core 16 0 p:$20 sw interrupt 0 core 17 0-2 p:$22 irqa reserved lvi 20 0-2 p:$28 low-voltage detector (power sense) pll 21 0-2 p:$2a pll fm 22 0-2 p:$2c fm access error interrupt fm 23 0-2 p:$2e fm command complete fm 24 0-2 p:$30 fm command, data and address buffers empty reserved flexcan 26 0-2 p:$34 flexcan bus off flexcan 27 0-2 p:$36 flexcan error flexcan 28 0-2 p:$38 flexcan wake up flexcan 29 0-2 p:$3a flexcan message buffer interrupt reserved gpioc 33 0-2 p:$42 gpio c gpiob 34 0-2 p:$44 gpio b gpioa 35 0-2 p:$46 gpio a reserved spi1 38 0-2 p:$4c spi 1 receiver full spi1 39 0-2 p:$4e spi 1 transmitter empty spi0 40 0-2 p:$50 spi 0 receiver full spi0 41 0-2 p:$52 spi 0 transmitter empty sci1 42 0-2 p:$54 sci 1 transmitter empty sci1 43 0-2 p:$56 sci 1transmitter idle reserved table 4-3 interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
56f8323 technical data, rev. 11.0 34 freescale semiconductor preliminary sci1 45 0-2 p:$5a sci 1 receiver error sci1 46 0-2 p:$5c sci 1 receiver full reserved dec0 49 0-2 p:$62 quadrature decoder #0 home switch or watchdog dec0 50 0-2 p:$64 quadrature decoder #0 index pulse reserved tmrc 56 0-2 p:$70 timer c channel 0 tmrc 57 0-2 p:$72 timer c channel 1 tmrc 58 0-2 p:$74 timer c channel 2 tmrc 59 0-2 p:$76 timer c channel 3 reserved tmra 64 0-2 p:$80 timer a channel 0 tmra 65 0-2 p:$82 timer a channel 1 tmra 66 0-2 p:$84 timer a channel 2 tmra 67 0-2 p:$86 timer a channel 3 sci0 68 0-2 p:$88 sci 0 transmitter empty sci0 69 0-2 p:$8a sci 0 transmitter idle reserved sci0 71 0-2 p:$8e sci 0 receiver error sci0 72 0-2 p:$90 sci 0 receiver full reserved adca 74 0-2 p:$94 adc a conversion complete / end of scan reserved adca 76 0-2 p:$98 adc a zero crossing or limit error reserved pwma 78 0-2 p:$9c reload pwm a reserved pwma 80 0-2 p:$a0 pwm a fault core 81 - 1 p:$a2 sw interrupt lp 82 0 - 2 p:$a4 1. two words are allocated for each entry in the vector table. this does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. if the vba is set to $0200, the first two locations of the vector table will overlay the chip reset addresses. table 4-3 interrupt vector table contents 1 (continued) peripheral vector number priority level vector base address + interrupt function
data map 56f8323 technical data, rev. 11.0 freescale semiconductor 35 preliminary 4.4 data map note: data flash is not available on the 56f8122 device. 4.5 flash memory map figure 4-1 illustrates the flash memory (fm) map on the system bus. flash memory is divided into three functional blocks. the program and boot memories reside on the program memory buses. they are controlled by one set of banked registers. data memory flash resides on the data memory buses and is controlled separately by its own set of banked registers. the top nine words of the program memory flash are treated as special memory locations. the content of these words is used to control the operation of the flash controller. because these words are part of the flash memory content, their state is maintained during power-down and reset. during chip initialization, the content of these memory locations is loaded into flash memory control registers, detailed in the flash memory chapter of the 56f8300 peripheral user manual . these configuration parameters are located between $00_3ff7 and $00_3fff. table 4-4 data memory map 1 1. all addresses are 16-bit word addresses. begin/end address memory allocation x:$ff ffff x:$ff ff00 eonce 256 locations allocated x:$ff feff x:$01 0000 reserved x:$00 ffff x:$00 f000 on-chip peripherals 4096 locations allocated x:$00 efff x:$00 2000 reserved x:$00 1fff x:$00 1000 on-chip data flash 8kb x:$00 0fff x:$00 0000 on-chip data ram 8kb 2 2. the data ram is organized as a 2k x 32-bit memory to allow single-cycle, long-word operations.
56f8323 technical data, rev. 11.0 36 freescale semiconductor preliminary figure 4-1 flash array memory maps table 4-5 shows the page and sector sizes used within each flash memory block on the chip. note: data flash is not available on the 56F8123 device. please see the 56f8300 peripheral user manual for additional flash information. table 4-5. flash memory partitions flash size sectors sector size page size program flash 32kb 16 1k x 16 bits 512 x 16 bits data flash 8kb 16 256 x 16 bits 256 x 16 bits boot flash 8kb 4 1k x 16 bits 256 x 16 bits boot_flash_start = $02_0000 boot_flash_start + $0fff block 0 odd block 0 even prog_flash_start + $00_3fff . . . 8kb boot reserved configure field prog_flash_start + $00_3ff7 prog_flash_start + $00_3ff6 32kb prog_flash_start = $00_0000 fm_prog_mem_top = $00_3fff block 0 odd (2 bytes) $00_0003 block 0 even (2 bytes) $00_0002 block 0 odd (2 bytes) $00_0001 block 0 even (2 bytes) $00_0000 fm_base + $14 banked registers unbanked registers 8kb fm_base + $00 data_flash_start + $0fff data_flash_start + $0000 data memory program memory note: data flash is not available in the 56F8123 device.
eonce memory map 56f8323 technical data, rev. 11.0 freescale semiconductor 37 preliminary 4.6 eonce memory map table 4-6 eonce memory map address register acronym register name reserved x:$ff ff8a oescr external signal control register reserved x:$ff ff8e obcntr breakpoint unit [0] counter reserved x:$ff ff90 obmsk (32 bits) breakpoint 1 unit [0] mask register x:$ff ff91 breakpoint 1 unit [0] mask register x:$ff ff92 obar2 (32 bits) breakpoint 2 unit [0] address register x:$ff ff93 breakpoint 2 unit [0] address register x:$ff ff94 obar1 (24 bits) breakpoint 1 unit [0] address register x:$ff ff95 breakpoint 1 unit [0] address register x:$ff ff96 obcr (24 bits) breakpoint unit [0] control register x:$ff ff97 breakpoint unit [0] control register x:$ff ff98 otb (21-24 bits/stage) trace buffer register stages x:$ff ff99 trace buffer register stages x:$ff ff9a otbpr (8 bits) trace buffer pointer register x:$ff ff9b otbcr trace buffer control register x:$ff ff9c obase (8 bits) peripheral base address register x:$ff ff9d osr status register x:$ff ff9e oscntr (24 bits) instruction step counter x:$ff ff9f instruction step counter x:$ff ffa0 ocr (bits) control register reserved x:$ff fffc oclsr (8 bits) core lock / unlock status register x:$ff fffd otxrxsr (8 bits) transmit and receive status and control register x:$ff fffe otx / orx (32 bits) transmit register / receive register x:$ff ffff otx1 / orx1 transmit register upper word receive register upper word
56f8323 technical data, rev. 11.0 38 freescale semiconductor preliminary 4.7 peripheral memory mapped registers on-chip peripheral registers are part of the data memory map on the 56800e series. these locations may be accessed with the same addressing modes used for ordinary data memory, except all peripheral registers should be read/written using word accesses only. table 4-7 summarizes base addresses for the set of peripherals on the 56f8323 and 56F8123 devices. peripherals are listed in order of the base address. the following tables list all of the peripheral registers required to control or access the peripherals. note: features in italics are not available in the 56F8123 device. table 4-7 data memory peripheral base address map summary peripheral prefix base address table number timer a tmra x:$00 f040 4-8 timer c tmrc x:$00 f0c0 4-9 pwm a pwma x:$00 f140 4-10 quadrature decoder 0 dec0 x:$00 f180 4-11 itcn itcn x:$00 f1a0 4-12 adc a adca x:$00 f200 4-13 temperature sensor tsensor x:$00 f270 4-14 sci #0 sci0 x:$00 f280 4-15 sci #1 sci1 x:$00 f290 4-16 spi #0 spi0 x:$00 f2a0 4-17 spi #1 spi1 x:$00 f2b0 4-18 cop cop x:$00 f2c0 4-19 pll, osc clkgen x:$00 f2d0 4-20 gpio port a gpioa x:$00 f2e0 4-21 gpio port b gpiob x:$00 f300 4-22 gpio port c gpioc x:$00 f310 4-23 sim sim x:$00 f350 4-24 power supervisor lvi x:$00 f360 4-25 fm fm x:$00 f400 4-26 flexcan fc x:$00 f800 4-27
peripheral memory mapped registers 56f8323 technical data, rev. 11.0 freescale semiconductor 39 preliminary table 4-8 quad timer a registers address map (tmra_base = $00 f040) register acronym address offset register description tmra0_cmp1 $0 compare register 1 tmra0_cmp2 $1 compare register 2 tmra0_cap $2 capture register tmra0_load $3 load register tmra0_hold $4 hold register tmra0_cntr $5 counter register tmra0_ctrl $6 control register tmra0_scr $7 status and control register tmra0_cmpld1 $8 comparator load register 1 tmra0_cmpld2 $9 comparator load register 2 tmra0_comscr $a comparator status and control register reserved tmra1_cmp1 $10 compare register 1 tmra1_cmp2 $11 compare register 2 tmra1_cap $12 capture register tmra1_load $13 load register tmra1_hold $14 hold register tmra1_cntr $15 counter register tmra1_ctrl $16 control register tmra1_scr $17 status and control register tmra1_cmpld1 $18 comparator load register 1 tmra1_cmpld2 $19 comparator load register 2 tmra1_comscr $1a comparator status and control register reserved tmra2_cmp1 $20 compare register 1 tmra2_cmp2 $21 compare register 2 tmra2_cap $22 capture register tmra2_load $23 load register tmra2_hold $24 hold register tmra2_cntr $25 counter register tmra2_ctrl $26 control register tmra2_scr $27 status and control register tmra2_cmpld1 $28 comparator load register 1
56f8323 technical data, rev. 11.0 40 freescale semiconductor preliminary tmra2_cmpld2 $29 comparator load register 2 tmra2_comscr $2a comparator status and control register reserved tmra3_cmp1 $30 compare register 1 tmra3_cmp2 $31 compare register 2 tmra3_cap $32 capture register tmra3_load $33 load register tmra3_hold $34 hold register tmra3_cntr $35 counter register tmra3_ctrl $36 control register tmra3_scr $37 status and control register tmra3_cmpld1 $38 comparator load register 1 tmra3_cmpld2 $39 comparator load register 2 tmra3_comscr $3a comparator status and control register table 4-9 quad timer c registers address map (tmrc_base = $00 f0c0) register acronym address offset register description tmrc0_cmp1 $0 compare register 1 tmrc0_cmp2 $1 compare register 2 tmrc0_cap $2 capture register tmrc0_load $3 load register tmrc0_hold $4 hold register tmrc0_cntr $5 counter register tmrc0_ctrl $6 control register tmrc0_scr $7 status and control register tmrc0_cmpld1 $8 comparator load register 1 tmrc0_cmpld2 $9 comparator load register 2 tmrc0_comscr $a comparator status and control register reserved tmrc1_cmp1 $10 compare register 1 tmrc1_cmp2 $11 compare register 2 tmrc1_cap $12 capture register tmrc1_load $13 load register table 4-8 quad timer a registers address map (continued) (tmra_base = $00 f040) register acronym address offset register description
peripheral memory mapped registers 56f8323 technical data, rev. 11.0 freescale semiconductor 41 preliminary tmrc1_hold $14 hold register tmrc1_cntr $15 counter register tmrc1_ctrl $16 control register tmrc1_scr $17 status and control register tmrc1_cmpld1 $18 comparator load register 1 tmrc1_cmpld2 $19 comparator load register 2 tmrc1_comscr $1a comparator status and control register reserved tmrc2_cmp1 $20 compare register 1 tmrc2_cmp2 $21 compare register 2 tmrc2_cap $22 capture register tmrc2_load $23 load register tmrc2_hold $24 hold register tmrc2_cntr $25 counter register tmrc2_ctrl $26 control register tmrc2_scr $27 status and control register tmrc2_cmpld1 $28 comparator load register 1 tmrc2_cmpld2 $29 comparator load register 2 tmrc2_comscr $2a comparator status and control register reserved tmrc3_cmp1 $30 compare register 1 tmrc3_cmp2 $31 compare register 2 tmrc3_cap $32 capture register tmrc3_load $33 load register tmrc3_hold $34 hold register tmrc3_cntr $35 counter register tmrc3_ctrl $36 control register tmrc3_scr $37 status and control register tmrc3_cmpld1 $38 comparator load register 1 tmrc3_cmpld2 $39 comparator load register 2 tmrc3_comscr $3a comparator status and control register table 4-9 quad timer c registers address map (continued) (tmrc_base = $00 f0c0) register acronym address offset register description
56f8323 technical data, rev. 11.0 42 freescale semiconductor preliminary table 4-10 pulse width modulator a registers address map (pwma_base = $00 f140) pwm is not available in the 56F8123 device register acronym address offset register description pwma_pmctrl $0 control register pwma_pmfctrl $1 fault control register pwma_pmfsa $2 fault status acknowledge register pwma_pmout $3 output control register pwma_pmcnt $4 counter register pwma_pwmcm $5 counter modulo register pwma_pwmval0 $6 value register 0 pwma_pwmval1 $7 value register 1 pwma_pwmval2 $8 value register 2 pwma_pwmval3 $9 value register 3 pwma_pwmval4 $a value register 4 pwma_pwmval5 $b value register 5 pwma_pmdeadtm $c dead time register pwma_pmdismap1 $d disable mapping register 1 pwma_pmdismap2 $e disable mapping register 2 pwma_pmcfg $f configure register pwma_pmccr $10 channel control register pwma_pmport $11 port register pwma_pmiccr $12 internal correction control register table 4-11 quadrature decoder 0 registers address map (dec0_base = $00 f180) quadrature decoder is not available in the 56F8123 device register acronym address offset register description dec0_deccr $0 decoder control register dec0_fir $1 filter interval register dec0_wtr $2 watchdog time-out register dec0_posd $3 position difference counter register dec0_posdh $4 position difference counter hold register dec0_rev $5 revolution counter register dec0_revh $6 revolution hold register dec0_upos $7 upper position counter register dec0_lpos $8 lower position counter register
peripheral memory mapped registers 56f8323 technical data, rev. 11.0 freescale semiconductor 43 preliminary dec0_uposh $9 upper position hold register dec0_lposh $a lower position hold register dec0_uir $b upper initialization register dec0_lir $c lower initialization register dec0_imr $d input monitor register table 4-12 interrupt control registers address map (itcn_base = $00 f1a0) register acronym address offset register description ipr0 $0 interrupt priority register 0 ipr1 $1 interrupt priority register 1 ipr2 $2 interrupt priority register 2 ipr3 $3 interrupt priority register 3 ipr4 $4 interrupt priority register 4 ipr5 $5 interrupt priority register 5 ipr6 $6 interrupt priority register 6 ipr7 $7 interrupt priority register 7 ipr8 $8 interrupt priority register 8 ipr9 $9 interrupt priority register 9 vba $a vector base address register fim0 $b fast interrupt match register 0 fival0 $c fast interrupt vector address low 0 register fivah0 $d fast interrupt vector address high 0 register fim1 $e fast interrupt match register 1 fival1 $f fast interrupt vector address low 1 register fivah1 $10 fast interrupt vector address high 1 register irqp0 $11 irq pending register 0 irqp1 $12 irq pending register 1 irqp2 $13 irq pending register 2 irqp3 $14 irq pending register 3 irqp4 $15 irq pending register 4 irqp5 $16 irq pending register 5 reserved ictl $1d interrupt control register table 4-11 quadrature decoder 0 registers address map (continued) (dec0_base = $00 f180) quadrature decoder is not available in the 56F8123 device register acronym address offset register description
56f8323 technical data, rev. 11.0 44 freescale semiconductor preliminary table 4-13 analog-to-digital converter registers address map (adca_base = $00 f200) register acronym address offset register description adca_cr1 $0 control register 1 adca_cr2 $1 control register 2 adca_zcc $2 zero crossing control register adca_lst 1 $3 channel list register 1 adca_lst 2 $4 channel list register 2 adca_sdis $5 sample disable register adca_stat $6 status register adca_lstat $7 limit status register adca_zcstat $8 zero crossing status register adca_rslt 0 $9 result register 0 adca_rslt 1 $a result register 1 adca_rslt 2 $b result register 2 adca_rslt 3 $c result register 3 adca_rslt 4 $d result register 4 adca_rslt 5 $e result register 5 adca_rslt 6 $f result register 6 adca_rslt 7 $10 result register 7 adca_llmt 0 $11 low limit register 0 adca_llmt 1 $12 low limit register 1 adca_llmt 2 $13 low limit register 2 adca_llmt 3 $14 low limit register 3 adca_llmt 4 $15 low limit register 4 adca_llmt 5 $16 low limit register 5 adca_llmt 6 $17 low limit register 6 adca_llmt 7 $18 low limit register 7 adca_hlmt 0 $19 high limit register 0 adca_hlmt 1 $1a high limit register 1 adca_hlmt 2 $1b high limit register 2 adca_hlmt 3 $1c high limit register 3 adca_hlmt 4 $1d high limit register 4 adca_hlmt 5 $1e high limit register 5 adca_hlmt 6 $1f high limit register 6 adca_hlmt 7 $20 high limit register 7
peripheral memory mapped registers 56f8323 technical data, rev. 11.0 freescale semiconductor 45 preliminary adca_ofs 0 $21 offset register 0 adca_ofs 1 $22 offset register 1 adca_ofs 2 $23 offset register 2 adca_ofs 3 $24 offset register 3 adca_ofs 4 $25 offset register 4 adca_ofs 5 $26 offset register 5 adca_ofs 6 $27 offset register 6 adca_ofs 7 $28 offset register 7 adca_power $29 power control register adca_cal $2a adc calibration register table 4-14 temperature sensor register address map (tsensor_base = $00 f270) temperature sensor is not available in the 56F8123 device register acronym address offset register description tsensor_cntl $0 control register table 4-15 serial communication interface 0 registers address map (sci0_base = $00 f280) register acronym address offset register description sci0_scibr $0 baud rate register sci0_scicr $1 control register reserved sci0_scisr $3 status register sci0_scidr $4 data register table 4-13 analog-to-digital converter registers address map (continued) (adca_base = $00 f200) register acronym address offset register description
56f8323 technical data, rev. 11.0 46 freescale semiconductor preliminary table 4-16 serial communication interface 1 registers address map (sci1_base = $00 f290) register acronym address offset register description sci1_scibr $0 baud rate register sci1_scicr $1 control register reserved sci1_scisr $3 status register sci1_scidr $4 data register table 4-17 serial peripheral interface 0 registers address map (spi0_base = $00 f2a0) register acronym address offset register description spi0_spscr $0 status and control register spi0_spdsr $1 data size register spi0_spdrr $2 data receive register spi0_spdtr $3 data transmitter register table 4-18 serial peripheral interface 1 registers address map (spi1_base = $00 f2b0) register acronym address offset register description spi1_spscr $0 status and control register spi1_spdsr $1 data size register spi1_spdrr $2 data receive register spi1_spdtr $3 data transmitter register table 4-19 computer operating properly registers address map (cop_base = $00 f2c0) register acronym address offset register description copctl $0 control register copto $1 time-out register copctr $2 counter register
peripheral memory mapped registers 56f8323 technical data, rev. 11.0 freescale semiconductor 47 preliminary table 4-20 clock generation module registers address map (clkgen_base = $00 f2d0) register acronym address offset register description pllcr $0 control register plldb $1 divide-by register pllsr $2 status register reserved shutdown $4 shutdown register osctl $5 oscillator control register table 4-21 gpioa registers address map (gpioa_base = $00 f2e0) register acronym address offset register description reset value gpioa_pur $0 pull-up enable register 0 x 0fff gpioa_dr $1 data register 0 x 0000 gpioa_ddr $2 data direction register 0 x 0000 gpioa_per $3 peripheral enable register 0 x 0fff gpioa_iar $4 interrupt assert register 0 x 0000 gpioa_ienr $5 interrupt enable register 0 x 0000 gpioa_ipolr $6 interrupt polarity register 0 x 0000 gpioa_ipr $7 interrupt pending register 0 x 0000 gpioa_iesr $8 interrupt edge-sensitive register 0 x 0000 gpioa_ppmode $9 push-pull mode register 0 x 0fff gpioa_rawdata $a raw data input register
56f8323 technical data, rev. 11.0 48 freescale semiconductor preliminary table 4-22 gpiob registers address map (gpiob_base = $00 f300) register acronym address offset register description reset value gpiob_pur $0 pull-up enable register 0 x 00ff gpiob_dr $1 data register 0 x 0000 gpiob_ddr $2 data direction register 0 x 0000 gpiob_per $3 peripheral enable register 0 x 00ff gpiob_iar $4 interrupt assert register 0 x 0000 gpiob_ienr $5 interrupt enable register 0 x 0000 gpiob_ipolr $6 interrupt polarity register 0 x 0000 gpiob_ipr $7 interrupt pending register 0 x 0000 gpiob_iesr $8 interrupt edge-sensitive register 0 x 0000 gpiob_ppmode $9 push-pull mode register 0 x 00ff gpiob_rawdata $a raw data input register table 4-23 gpioc registers address map (gpioc_base = $00 f310) register acronym address offset register description reset value gpioc_pur $0 pull-up enable register 0 x 007c gpioc_dr $1 data register 0 x 0000 gpioc_ddr $2 data direction register 0 x 0000 gpioc_per $3 peripheral enable register 0 x 007f gpioc_iar $4 interrupt assert register 0 x 0000 gpioc_ienr $5 interrupt enable register 0 x 0000 gpioc_ipolr $6 interrupt polarity register 0 x 0000 gpioc_ipr $7 interrupt pending register 0 x 0000 gpioc_iesr $8 interrupt edge-sensitive register 0 x 0000 gpioc_ppmode $9 push-pull mode register 0 x 007f gpioc_rawdata $a raw data input register
peripheral memory mapped registers 56f8323 technical data, rev. 11.0 freescale semiconductor 49 preliminary table 4-24 system integration module registers address map (sim_base = $00 f350) register acronym address offset register description sim_control $0 control register sim_rststs $1 reset status register sim_scr0 $2 software control register 0 sim_scr1 $3 software control register 1 sim_scr2 $4 software control register 2 sim_scr3 $5 software control register 3 sim_msh_id $6 most significant half jtag id sim_lsh_id $7 least significant half jtag id sim_pudr $8 pull-up disable register reserved sim_clkosr $a clock out select register sim_gps $b gpio peripheral select register sim_pce $c peripheral clock enable register sim_isalh $d i/o short address location high register sim_isall $e i/o short address location low register table 4-25 power supervisor registers address map (lvi_base = $00 f360) register acronym address offset register description lvi_control $0 control register lvi_status $1 status register
56f8323 technical data, rev. 11.0 50 freescale semiconductor preliminary table 4-26 flash module registers address map (fm_base = $00 f400) register acronym address offset register description fmclkd $0 clock divider register fmmcr $1 module control register reserved fmsech $3 security high half register fmsecl $4 security low half register reserved reserved fmprot $10 protection register (banked) fmprotb $11 protection boot register (banked) reserved fmustat $13 user status register (banked) fmcmd $14 command register (banked) reserved reserved fmopt 0 $1a 16-bit information option register 0 hot temperature adc reading of temperature sensor; value set during factory test fmopt 1 $1b 16-bit information option register 1 trim cap setting of the relaxation oscillator fmopt 2 $1c 16-bit information option register 2 room temperature adc reading of temperature sensor; value set during factory test table 4-27 flexcan registers address map (fc_base = $00 f800) flexcan is not available in the 56F8123 device register acronym address offset register description fcmcr $0 module configuration register reserved fcctl0 $3 control register 0 register fcctl1 $4 control register 1 register fctmr $5 free-running timer register fcmaxmb $6 maximum message buffer configuration register reserved
peripheral memory mapped registers 56f8323 technical data, rev. 11.0 freescale semiconductor 51 preliminary fcrxgmask_h $8 receive global mask high register fcrxgmask_l $9 receive global mask low register fcrx14mask_h $a receive buffer 14 mask high register fcrx14mask_l $b receive buffer 14 mask low register fcrx15mask_h $c receive buffer 15 mask high register fcrx15mask_l $d receive buffer 15 mask low register reserved fcstatus $10 error and status register fcimask1 $11 interrupt masks 1 register fciflag1 $12 interrupt flags 1 register fcr/t_error_cntrs $13 receive and transmit error counters register reserved reserved reserved fcmb0_control $40 message buffer 0 control / status register fcmb0_id_high $41 message buffer 0 id high register fcmb0_id_low $42 message buffer 0 id low register fcmb0_data $43 message buffer 0 data register fcmb0_data $44 message buffer 0 data register fcmb0_data $45 message buffer 0 data register fcmb0_data $46 message buffer 0 data register reserved fcmsb1_control $48 message buffer 1 control / status register fcmsb1_id_high $49 message buffer 1 id high register fcmsb1_id_low $4a message buffer 1 id low register fcmb1_data $4b message buffer 1 data register fcmb1_data $4c message buffer 1 data register fcmb1_data $4d message buffer 1 data register fcmb1_data $4e message buffer 1 data register reserved fcmb2_control $50 message buffer 2 control / status register fcmb2_id_high $51 message buffer 2 id high register fcmb2_id_low $52 message buffer 2 id low register table 4-27 flexcan registers address map (continued) (fc_base = $00 f800) flexcan is not available in the 56F8123 device register acronym address offset register description
56f8323 technical data, rev. 11.0 52 freescale semiconductor preliminary fcmb2_data $53 message buffer 2 data register fcmb2_data $54 message buffer 2 data register fcmb2_data $55 message buffer 2 data register fcmb2_data $56 message buffer 2 data register reserved fcmb3_control $58 message buffer 3 control / status register fcmb3_id_high $59 message buffer 3 id high register fcmb3_id_low $5a message buffer 3 id low register fcmb3_data $5b message buffer 3 data register fcmb3_data $5c message buffer 3 data register fcmb3_data $5d message buffer 3 data register fcmb3_data $5e message buffer 3 data register reserved fcmb4_control $60 message buffer 4 control / status register fcmb4_id_high $61 message buffer 4 id high register fcmb4_id_low $62 message buffer 4 id low register fcmb4_data $63 message buffer 4 data register fcmb4_data $64 message buffer 4 data register fcmb4_data $65 message buffer 4 data register fcmb4_data $66 message buffer 4 data register reserved fcmb5_control $68 message buffer 5 control / status register fcmb5_id_high $69 message buffer 5 id high register fcmb5_id_low $6a message buffer 5 id low register fcmb5_data $6b message buffer 5 data register fcmb5_data $6c message buffer 5 data register fcmb5_data $6d message buffer 5 data register fcmb5_data $6e message buffer 5 data register reserved fcmb6_control $70 message buffer 6 control / status register fcmb6_id_high $71 message buffer 6 id high register fcmb6_id_low $72 message buffer 6 id low register fcmb6_data $73 message buffer 6 data register table 4-27 flexcan registers address map (continued) (fc_base = $00 f800) flexcan is not available in the 56F8123 device register acronym address offset register description
peripheral memory mapped registers 56f8323 technical data, rev. 11.0 freescale semiconductor 53 preliminary fcmb6_data $74 message buffer 6 data register fcmb6_data $75 message buffer 6 data register fcmb6_data $76 message buffer 6 data register reserved fcmb7_control $78 message buffer 7 control / status register fcmb7_id_high $79 message buffer 7 id high register fcmb7_id_low $7a message buffer 7 id low register fcmb7_data $7b message buffer 7 data register fcmb7_data $7c message buffer 7 data register fcmb7_data $7d message buffer 7 data register fcmb7_data $7e message buffer 7 data register reserved fcmb8_control $80 message buffer 8 control / status register fcmb8_id_high $81 message buffer 8 id high register fcmb8_id_low $82 message buffer 8 id low register fcmb8_data $83 message buffer 8 data register fcmb8_data $84 message buffer 8 data register fcmb8_data $85 message buffer 8 data register fcmb8_data $86 message buffer 8 data register reserved fcmb9_control $88 message buffer 9 control / status register fcmb9_id_high $89 message buffer 9 id high register fcmb9_id_low $8a message buffer 9 id low register fcmb9_data $8b message buffer 9 data register fcmb9_data $8c message buffer 9 data register fcmb9_data $8d message buffer 9 data register fcmb9_data $8e message buffer 9 data register reserved fcmb10_control $90 message buffer 10 control / status register fcmb10_id_high $91 message buffer 10 id high register fcmb10_id_low $92 message buffer 10 id low register fcmb10_data $93 message buffer 10 data register fcmb10_data $94 message buffer 10 data register table 4-27 flexcan registers address map (continued) (fc_base = $00 f800) flexcan is not available in the 56F8123 device register acronym address offset register description
56f8323 technical data, rev. 11.0 54 freescale semiconductor preliminary fcmb10_data $95 message buffer 10 data register fcmb10_data $96 message buffer 10 data register reserved fcmb11_control $98 message buffer 11 control / status register fcmb11_id_high $99 message buffer 11 id high register fcmb11_id_low $9a message buffer 11 id low register fcmb11_data $9b message buffer 11 data register fcmb11_data $9c message buffer 11 data register fcmb11_data $9d message buffer 11 data register fcmb11_data $9e message buffer 11 data register reserved fcmb12_control $a0 message buffer 12 control / status register fcmb12_id_high $a1 message buffer 12 id high register fcmb12_id_low $a2 message buffer 12 id low register fcmb12_data $a3 message buffer 12 data register fcmb12_data $a4 message buffer 12 data register fcmb12_data $a5 message buffer 12 data register fcmb12_data $a6 message buffer 12 data register reserved fcmb13_control $a8 message buffer 13 control / status register fcmb13_id_high $a9 message buffer 13 id high register fcmb13_id_low $aa message buffer 13 id low register fcmb13_data $ab message buffer 13 data register fcmb13_data $ac message buffer 13 data register fcmb13_data $ad message buffer 13 data register fcmb13_data $ae message buffer 13 data register reserved fcmb14_control $b0 message buffer 14 control / status register fcmb14_id_high $b1 message buffer 14 id high register fcmb14_id_low $b2 message buffer 14 id low register fcmb14_data $b3 message buffer 14 data register fcmb14_data $b4 message buffer 14 data register fcmb14_data $b5 message buffer 14 data register table 4-27 flexcan registers address map (continued) (fc_base = $00 f800) flexcan is not available in the 56F8123 device register acronym address offset register description
factory programmed memory 56f8323 technical data, rev. 11.0 freescale semiconductor 55 preliminary 4.8 factory programmed memory the boot flash memory block is programmed during manufacturing with a default serial bootloader program. the serial bootloader application can be used to load a user application into the program and data flash ( not available in the 56F8123 ) memories of the device. the 56f83xx sci/can bootloader user manual provides detailed information on this firmware. an application note, production flash programming, details how the serial bootloader program can be used to perform production flash programming of the on-board flash memories as well as other optional methods. like all the flash memory blocks, the boot flash can be erased and programmed by the user. the serial bootloader application is programmed as an aid to the end user, but is not required to be used or maintained in the boot flash memory. part 5 interrupt controller (itcn) 5.1 introduction the interrupt controller (itcn) module is used to arbitrate between various interrupt requests (irqs), to signal to the 56800e core when an interrupt of sufficient priority exists, and to what address to jump in order to service this interrupt. fcmb14_data $b6 message buffer 14 data register reserved fcmb15_control $b8 message buffer 15 control / status register fcmb15_id_high $b9 message buffer 15 id high register fcmb15_id_low $ba message buffer 15 id low register fcmb15_data $bb message buffer 15 data register fcmb15_data $bc message buffer 15 data register fcmb15_data $bd message buffer 15 data register fcmb15_data $be message buffer 15 data register reserved table 4-27 flexcan registers address map (continued) (fc_base = $00 f800) flexcan is not available in the 56F8123 device register acronym address offset register description
56f8323 technical data, rev. 11.0 56 freescale semiconductor preliminary 5.2 features the itcn module design includes these distinctive features: ? programmable priority levels for each irq ? two programmable fast interrupts ? notification to sim module to restart clocks out of wait and stop modes ? drives initial address on the address bus after reset for further information, see table 4-3 , interrupt vector table contents. 5.3 functional description the interrupt controller is a slave on the ipbus. it contains registers allowing each of the 82 interrupt sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. next, all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the active interrupt requests for that level. within a given priority level, 0 is the highest priority, while number 81 is the lowest. 5.3.1 normal interrupt handling once the itcn has determined that an interrupt is to be serviced and which interrupt has the highest priority, an interrupt vector address is generated. normal interrupt handling concatenates the vba and the vector number to determine the vector address. in this way, an offset is generated into the vector table for each interrupt. 5.3.2 interrupt nesting interrupt exceptions may be nested to allow an irq of higher priority than the current exception to be serviced. the following tables define the nesting requirements for each priority level. table 5-1 interrupt mask bit definition sr[9] 1 1. core status register bits indicating current interrupt mask within the core. sr[8] 1 permitted exceptions masked exceptions 0 0 priorities 0, 1, 2, 3 none 0 1 priorities 1, 2, 3 priority 0 1 0 priorities 2, 3 priorities 0, 1 1 1 priority 3 priorities 0, 1, 2
functional description 56f8323 technical data, rev. 11.0 freescale semiconductor 57 preliminary 5.3.3 fast interrupt handling fast interrupts are described in the dsp56800e reference manual . the interrupt controller recognizes fast interrupts before the core does. a fast interrupt is defined (to the itcn) by: 1. setting the priority of the interrupt as level 2, with the appropriate field in the ipr registers 2. setting the fimn register to the appropriate vector number 3. setting the fivaln and fivahn registers with the address of the code for the fast interrupt when an interrupt occurs, its vector number is compared with the fim0 and fim1 register values. if a match occurs, and it is a level 2 interrupt, the itcn handles it as a fast interrupt. the itcn takes the vector address from the appropriate fivaln and fivahn registers, instead of generating an address that is an offset from the vba. the core then fetches the instruction from the indicated vector adddress and if it is not a jsr, the core starts its fast interrupt handling. table 5-2. interrupt priority encoding ipic_level[1:0] 1 1. see ipic field definition in section 5.6.30.2 current interrupt priority level required nested exception priority 00 no interrupt or swilp priorities 0, 1, 2, 3 01 priority 0 priorities 1, 2, 3 10 priority 1 priorities 2, 3 11 priorities 2 or 3 priority 3
56f8323 technical data, rev. 11.0 58 freescale semiconductor preliminary 5.4 block diagram figure 5-1 interrupt controller block diagram 5.5 operating modes the itcn module design contains two major modes of operation: ? functional mode the itcn is in this mode by default. ? wait and stop modes during wait and stop modes, the system clocks and the 56800e core are turned off. the itcn will signal a pending irq to the system integration module (sim) to restart the clocks and service the irq. an irq can only wake up the core if the irq is enabled prior to entering the wait or stop mode. also, the irqa signal automatically becomes low-level sensitive in these modes, even if the control register bits are set to make them falling-edge sensitive. this is because there is no clock available to detect the falling edge. a peripheral which requires a clock to generate interrupts will not be able to generate interrupts during stop mode. the flexcan module can wake the device from stop mode, and a reset will do just that, or irqa and irqb can wake it up. priority level 2 -> 4 decode int1 priority level 2 -> 4 decode int82 level 0 82 -> 7 priority encoder any0 level 3 82 -> 7 priority encoder any3 int vab ipic control 7 7 pic_en iack sr[9:8]
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 59 preliminary 5.6 register descriptions a register address is the sum of a base address and an address offset. the base address is defined at the system level and the address offset is defined at the module level. the itcn peripheral has 24 registers. table 5-3 itcn register summary (itcn_base = $00 f1a0) register acronym base address + register name section location ipr0 $0 interrupt priority register 0 5.6.1 ipr1 $1 interrupt priority register 1 5.6.2 ipr2 $2 interrupt priority register 2 5.6.3 ipr3 $3 interrupt priority register 3 5.6.4 ipr4 $4 interrupt priority register 4 5.6.5 ipr5 $5 interrupt priority register 5 5.6.6 ipr6 $6 interrupt priority register 6 5.6.7 ipr7 $7 interrupt priority register 7 5.6.8 ipr8 $8 interrupt priority register 8 5.6.9 ipr9 $9 interrupt priority register 9 5.6.10 vba $a vector base address register 5.6.11 fim0 $b fast interrupt 0 match register 5.6.12 fival0 $c fast interrupt 0 vector address low register 5.6.13 fivah0 $d fast interrupt 0 vector address high register 5.6.14 fim1 $e fast interrupt 1 match register 5.6.15 fival1 $f fast interrupt 1 vector address low register 5.6.16 fivah1 $10 fast interrupt 1 vector address high register 5.6.17 irqp0 $11 irq pending register 0 5.6.18 irqp1 $12 irq pending register 1 5.6.19 irqp2 $13 irq pending register 2 5.6.20 irqp3 $14 irq pending register 3 5.6.21 irqp4 $15 irq pending register 4 5.6.22 irqp5 $16 irq pending register 5 5.6.23 reserved ictl $1d interrupt control register 5.6.30
56f8323 technical data, rev. 11.0 60 freescale semiconductor preliminary figure 5-2 itcn register map summary add. offset register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 ipr0 r 0 0 bkpt_ u0 ipl stpcnt ipl 0 0 0 0 0 0 0 0 0 0 w $1 ipr1 r 0 0 0 0 0 0 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl w $2 ipr2 r fmcbe ipl fmcc ipl fmerr ipl lock ipl lvi ipl 0 0 0 0 irqa ipl w $3 ipr3 r 0 0 0 0 0 0 fcmsgbuf ipl fcwkup ipl fcerr ipl fcboff ipl 0 0 w $4 ipr4 r spi0_rcv ipl spi1_xmit ipl spi1_rcv ipl 0 0 0 0 gpioa ipl gpiob ipl gpioc ipl w $5 ipr5 r 0 0 0 0 sci1_rcv ipl sci1_rerr ipl 0 0 sci1_tidl ipl sci1_xmit ipl spi0_xmit ipl w $6 ipr6 r tmrc0 ipl 0 0 0 0 0 0 0 0 0 0 dec0_xirq ipl dec0_hirq ipl w 0 0 $7 ipr7 r tmra0 ipl 0 0 0 0 0 0 0 0 tmrc3 ipl tmrc2 ipl tmrc1 ipl w $8 ipr8 r sci0_rcv ipl sci0_rerr ipl 0 0 sci0_tidl ipl sci0_xmit ipl tmra3 ipl tmra2 ipl tmra1 ipl w $9 ipr9 r pwma f ipl 0 0 pwma_rl ipl 0 0 adca_zc ipl 0 0 adca_cc ipl 0 0 w $a vba r 0 0 0 vector base address w $b fim0 r 0 0 0 0 0 0 0 0 0 fast interrupt 0 w $c fival0 r fast interrupt 0 vector address low w $d fivah0 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high w $e fim1 r 0 0 0 0 0 0 0 0 0 fast interrupt 1 w $f fival1 r fast interrupt 1 vector address low w $10 fivah1 r 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high w $11 irqp0 r pending [16:2] 1 w $12 irqp1 r pending [32:17] w $13 irqp2 r pending [48:33] w $14 irqp3 r pending [64:49] w $15 irqp4 r pending [80:65] w $16 irqp5 r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 pend- ing [81] w reserved $1d ictl r int ipic vab int_ dis 1 0 irqa state 0 irqa edg w = reserved
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 61 preliminary 5.6.1 interrupt priority register 0 (ipr0) figure 5-3 interrupt priority register 0 (ipr0) 5.6.1.1 reservedbits 15C14 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.1.2 eonce breakpoint unit 0 interrupt priority level (bkpt_u0 ipl) bits13C12 this field is used to set the interrupt priority levels for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.3 eonce step counter interrupt priority level (stpcnt ipl) bits 11C10 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.1.4 reservedbits 9C0 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.2 interrupt priority register 1 (ipr1) figure 5-4 interrupt priority register 1 (ipr1) base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 bkpt_u0 ipl stpcnt ipl 0 0 0 0 0 0 0 0 0 0 write reset 0 0 0 0 0 0 0 000000000 base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 rx_reg ipl tx_reg ipl trbuf ipl write reset 0000000000000000
56f8323 technical data, rev. 11.0 62 freescale semiconductor preliminary 5.6.2.1 reservedbits 15C6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.2.2 eonce receive register full interrupt priority level (rx_reg ipl)bits 5C4 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.2.3 eonce transmit register empty interrupt priority level (tx_reg ipl)bits 3C2 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.2.4 eonce trace buffer interrupt priority level (trbuf ipl) bits 1C0 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 1 through 3. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 1 ? 10 = irq is priority level 2 ? 11 = irq is priority level 3 5.6.3 interrupt priority register 2 (ipr2) figure 5-5 interrupt priority register 2 (ipr2) base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fmcbe ipl fmcc ipl fmerr ipl lock ipl lvi ipl 0 0 0 0 irqa ipl write reset 0000000000000000
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 63 preliminary 5.6.3.1 flash memory command, data, address buffers empty interrupt priority level (fmcbe ipl)bits 15C14 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.2 flash memory command complete priority level (fmcc ipl)bits 13C12 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.3 flash memory error interrupt priority level (fmerr ipl)bits 11C10 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.4 pll loss of lock interrupt priority level (lock ipl)bits 9C8 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
56f8323 technical data, rev. 11.0 64 freescale semiconductor preliminary 5.6.3.5 low voltage detector interrupt priority level (lvi ipl)bits 7C6 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.3.6 reservedbits 5C2 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.3.7 external irq a interrupt priority level (irqa ipl)bits 1C0 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. it is disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4 interrupt priority register 3 (ipr3) figure 5-6 interrupt priority register 3 (ipr3) 5.6.4.1 reservedbits 15C10 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.4.2 flexcan message buffer interrupt priority level (fcmsgbuf ipl)bits 9C8 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 fcmsgbuf ipl fcwkup ipl fcerr ipl fcboff ipl 0 0 write reset 000000 0 0 0 0 0 0 0 0 0 0
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 65 preliminary 5.6.4.3 flexcan wake up interrupt priority level (fcwkup ipl) bits 7C6 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.4 flexcan error interrupt priority level (fcerr ipl) bits 5C4 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.5 flexcan bus off interrupt priority level (fcboff ipl) bits 3C2 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.4.6 reservedbits 1C0 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.5 interrupt priority register 4 (ipr4) figure 5-7 interrupt priority register 4 (ipr4) base + $4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read spi0_rcv ipl spi1_xmit ipl spi1_rcv ipl 0 0 0 0 gpioa ipl gpiob ipl gpioc ipl write reset 0000000000000000
56f8323 technical data, rev. 11.0 66 freescale semiconductor preliminary 5.6.5.1 spi0 receiver full interrupt priority level (spi0_rcv ipl) bits 15C14 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.2 spi1 transmit empty interrupt priority level (spi1_xmit ipl) bits 13C12 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.3 spi1 receiver full interrupt priority level (spi1_rcv ipl) bits 11C10 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.4 reservedbits 9C6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.5.5 gpioa interrupt priority level (gpioa ipl)bits 5C4 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 67 preliminary 5.6.5.6 gpiob interrupt priority level (gpiob ipl)bits 3C2 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.5.7 gpioc interrupt priority level (gpioc ipl)bits 1C0 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6 interrupt priority register 5 (ipr5) figure 5-8 interrupt priority register 5 (ipr5) 5.6.6.1 reservedbits 15C12 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.6.2 sci1 receiver full interrupt priority level (sci1_rcv ipl) bits 11C10 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 sci1_rcv ipl sci1_rerr ipl 0 0 sci1_tidl ipl sci1_xmit ipl spi0_xmit ipl write reset 000000 0 0 00000000
56f8323 technical data, rev. 11.0 68 freescale semiconductor preliminary 5.6.6.3 sci1 receiver error interrupt priority level (sci1_rerr ipl) bits 9C8 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.4 reservedbits 7C6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.6.5 sci1 transmitter idle interrupt priority level (sci1_tidl ipl) bits 5C4 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.6 sci1 transmitter empty interrupt priority level (sci1_xmit ipl) bits 3C2 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.6.7 spi0 transmitter empty interrupt priority level (spi0_xmit ipl) bits 1C0 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 69 preliminary 5.6.7 interrupt priority register 6 (ipr6) figure 5-9 interrupt priority register 6 (ipr6) 5.6.7.1 timer c, channel 0 interrupt priority level (tmrc0 ipl) bits 15C14 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.2 reservedbits 13C4 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.7.3 quadrature decoder 0, index pulse interrupt priority level (dec0_xirq ipl)bits 3C2 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.7.4 quadrature decoder 0, home signal transition or watchdog timer interrupt priority level (dec0_hirq ipl)bits 1C0 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tmrc0 ipl 0 0 0 0 0 0 0 0 0 0 dec0_xirq ipl dec0_hirq ipl write reset 0000000000000000
56f8323 technical data, rev. 11.0 70 freescale semiconductor preliminary 5.6.8 interrupt priority register 7 (ipr7) figure 5-10 interrupt priority register (ipr7) 5.6.8.1 timer a, channel 0 interrupt priority level (tmra0 ipl) bits 15C14 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.2 reservedbits 13C6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.8.3 timer c, channel 3 interrupt priority level (tmrc3 ipl)bits 5C4 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.8.4 timer c, channel 2 interrupt priority level (tmrc2 ipl)bits 3C2 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read tmra0 ipl 0 0 0 0 0 0 0 0 tmrc3 ipl tmrc2 ipl tmrc1 ipl write reset 0000000000000000
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 71 preliminary 5.6.8.5 timer c, channel 1 interrupt priority level (tmrc1 ipl)bits 1C0 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9 interrupt priority register 8 (ipr8) figure 5-11 interrupt priority register 8 (ipr8) 5.6.9.1 sci0 receiver full interrupt priority level (sci0 rcv ipl) bits 15C14 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.2 sci0 receiver error interrupt priority level (sci0 rerr ipl) bits 13C12 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.3 reservedbits 11C10 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read sci0_rcv ipl sci0_rerr ipl 0 0 sci0_tidl ipl sci0_xmit ipl tmra3 ipl tmra2 ipl tmra1 ipl write reset 0000000000000000
56f8323 technical data, rev. 11.0 72 freescale semiconductor preliminary 5.6.9.4 sci0 transmitter idle interrupt priority level (sci0 tidl ipl) bits 9C8 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.5 sci0 transmitter empty interrupt priority level (sci0 xmit ipl) bits 7C6 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.6 timer a, channel 3 interrupt priority level (tmra 3 ipl)bits 5C4 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.9.7 timer a, channel 2 interrupt priority level (tmra 2 ipl)bits 3C2 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 73 preliminary 5.6.9.8 timer a, channel 1 interrupt priority level (tmra 1 ipl)bits 1C0 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10 interrupt priority register 9 (ipr9) figure 5-12 interrupt priority register 9 (ipr9) 5.6.10.1 pwm a fault interrupt priority level (pwma f ipl)bits 15C14 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.2 reservedbits 13C12 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.10.3 reload pwm a interrupt priority level (pwma_rl ipl) bits 11C10 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.4 reservedbits 9C8 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. base + $9 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pwma f ipl 0 0 pwma_rl ipl 0 0 adca_zc ipl 0 0 adca_cc ipl 0 0 write reset 0000000000000000
56f8323 technical data, rev. 11.0 74 freescale semiconductor preliminary 5.6.10.5 adc a zero crossing or limit error interrupt priority level (adca_zc ipl)bits 7C6 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.6 reservedbits 5C4 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.10.7 adc a conversion complete interrupt priority level (adca_cc ipl)bits 3C2 this field is used to set the interrupt priority level for irqs. this irq is limited to priorities 0 through 2. they are disabled by default. ? 00 = irq disabled (default) ? 01 = irq is priority level 0 ? 10 = irq is priority level 1 ? 11 = irq is priority level 2 5.6.10.8 reservedbits 1C0 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.11 vector base address register (vba) figure 5-13 vector base address register (vba) 5.6.11.1 reservedbits 15C13 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.11.2 interrupt vector base address (vector base address) bits 12C0 the contents of this register determine the location of the vector address table. the value in this register is used as the upper 13 bits of the interrupt vector address. the lower eight bits of the isr address are determined based upon the highest-priority interrupt; see part 5.3.1 for details. base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 vector base address write reset 0000000000000000
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 75 preliminary 5.6.12 fast interrupt 0 match register (fim0) figure 5-14 fast interrupt 0 match register (fim0) 5.6.12.1 reservedbits 15C7 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.12.2 fast interrupt 0 vector number (fast interrupt 0)bits 6C0 this value determines which irq will be a fast interrupt 0. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first; for details, see part 5.3.3 . irqs used as fast interrupts must be set to priority level 2. unexpected results will occur if a fast interrupt vector is set to any other priority. fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector number of each irq, refer to table 4-3 . 5.6.13 fast interrupt 0 vector address low register (fival0) figure 5-15 fast interrupt 0 vector address low register (fival0) 5.6.13.1 fast interrupt 0 vector address low (fival0)bits 15C0 the lower 16 bits of the vector address used for fast interrupt 0. this register is combined with fivah0 to form the 21-bit vector address for fast interrupt 0 defined in the fim0 register. 5.6.14 fast interrupt 0 vector address high register (fivah0) figure 5-16 fast interrupt 0 vector address high register (fivah0) base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 0 write reset 0000000000000000 base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 0 vector address low write reset 0000000000000000 base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 0 vector address high write reset 0000000000000000
56f8323 technical data, rev. 11.0 76 freescale semiconductor preliminary 5.6.14.1 reservedbits 15C5 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.14.2 fast interrupt 0 vector address high (fivah0)bits 4C0 the upper five bits of the vector address used for fast interrupt 0. this register is combined with fival0 to form the 21-bit vector address for fast interrupt 0 defined in the fim0 register. 5.6.15 fast interrupt 1 match register (fim1) figure 5-17 fast interrupt 1 match register (fim1) 5.6.15.1 reservedbits 15C7 this bit field is reserved or not implemented. it is read as 0, but cannot be modified by writing. 5.6.15.2 fast interrupt 1 vector number (fast interrupt 1)bits 6C0 this value determines which irq will be a fast interrupt 1. fast interrupts vector directly to a service routine based on values in the fast interrupt vector address registers without having to go to a jump table first; for details, see part 5.3.3 . irqs used as fast interrupts must be set to priority level 2. unexpected results will occur if a fast interrupt vector is set to any other priority. fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. fast interrupt 0 has priority over fast interrupt 1. to determine the vector number of each irq, refer to table 4-3 . 5.6.16 fast interrupt 1 vector address low register (fival1) figure 5-18 fast interrupt 1 vector address low register (fival1) 5.6.16.1 fast interrupt 1 vector address low (fival1)bits 15C0 the lower 16 bits of the vector address used for fast interrupt 1. this register is combined with fivah1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 fast interrupt 1 write reset 0000000000000000 base + $f 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read fast interrupt 1 vector address low write reset 0000000000000000
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 77 preliminary 5.6.17 fast interrupt 1 vector address high register (fivah1) figure 5-19 fast interrupt 1 vector address high register (fivah1) 5.6.17.1 reservedbits 15C5 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.17.2 fast interrupt 1 vector address high (fivah1)bits 4C0 the upper five bits of the vector address are used for fast interrupt 1. this register is combined with fival1 to form the 21-bit vector address for fast interrupt 1 defined in the fim1 register. 5.6.18 irq pending 0 register (irqp0) figure 5-20 irq pending 0 register (irqp0) 5.6.18.1 irq pending (pending)bits 16C2 this register combines with the other five to represent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.18.2 reservedbit 0 this bit is reserved or not implemented. it is read as 1 and cannot be modified by writing. 5.6.19 irq pending 1 register (irqp1) figure 5-21 irq pending 1 register (irqp1) base + $10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 0 fast interrupt 1 vector address high write reset 0000000000000000 base + $11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [16:2] 1 write reset 1111111111111111 $base + $12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [32:17] write reset 1111111111111111
56f8323 technical data, rev. 11.0 78 freescale semiconductor preliminary 5.6.19.1 irq pending (pending)bits 32C17 this register combines with the other five to represent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.20 irq pending 2 register (irqp2) figure 5-22 irq pending 2 register (irqp2) 5.6.20.1 irq pending (pending)bits 48C33 this register combines with the other five to represent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.21 irq pending 3 register (irqp3) figure 5-23 irq pending 3 register (irqp3) 5.6.21.1 irq pending (pending)bits 64C49 this register combines with the other five to represent the pending irqs for interrupt vector numbers two through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number base + $13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [48:33] write reset 1111111111111111 base + $14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [64:49] write reset 1111111111111111
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 79 preliminary 5.6.22 irq pending 4 register (irqp4) figure 5-24 irq pending 4 register (irqp4) 5.6.22.1 irq pending (pending)bits 80C65 this register combines with the other five to represent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.23 irq pending 5 register (irqp5) figure 5-25 irq pending register 5 (irqp5) 5.6.23.1 reservedbits 96C82 this bit field is reserved or not implemented. the bits are read as 1 and cannot be modified by writing. 5.6.23.2 irq pending (pending)bit 81 this register combines with the other five to represent the pending irqs for interrupt vector numbers 2 through 81. ? 0 = irq pending for this vector number ? 1 = no irq pending for this vector number 5.6.24 reserved base + 17 5.6.25 reserved base + 18 5.6.26 reserved base + 19 5.6.27 reserved base + 1a base + $15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read pending [80:65] write reset 1111111111111111 base + $16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 pend- ing [81] write reset 111111111111111 1
56f8323 technical data, rev. 11.0 80 freescale semiconductor preliminary 5.6.28 reserved base + 1b 5.6.29 reserved base + 1c 5.6.30 itcn control register (ictl) figure 5-26 itcn control register (ictl) 5.6.30.1 interrupt (int)bit 15 this read-only bit reflects the state of the interrupt to the 56800e core. ? 0 = no interrupt is being sent to the 56800e core ? 1 = an interrupt is being sent to the 56800e core 5.6.30.2 interrupt priority level (ipic)bits 14C13 these read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800e core at the time the last irq was taken. this field is only updated when the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be updated before the original interrupt service routine can read it. ? 00 = required nested exception priority levels are 0, 1, 2, or 3 ? 01 = required nested exception priority levels are 1, 2, or 3 ? 10 = required nested exception priority levels are 2 or 3 ? 11 = required nested exception priority level is 3 5.6.30.3 vector number - vector address bus (vab)bits 12C6 this read-only field shows the vector number (vab[7:1]) used at the time the last irq was taken. this field is only updated when the 56800e core jumps to a new interrupt service routine. note: nested interrupts may cause this field to be updated before the original interrupt service routine can read it. 5.6.30.4 interrupt disable (int_dis)bit 5 this bit allows all interrupts to be disabled. ? 0 = normal operation (default) ? 1 = all interrupts disabled base + $1d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read int ipic vab int_dis 1 0 irqa state 0 irqa edg write reset 0 0 0 1000000 0 1 1 1 0 0
resets 56f8323 technical data, rev. 11.0 freescale semiconductor 81 preliminary 5.6.30.5 reservedbit 4 this bit field is reserved or not implemented. it is read as 1 and cannot be modified by writing. 5.6.30.6 reservedbit 3 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.30.7 irqa state pin (irqa state)bit 2 this read-only bit reflects the state of the external irqa pin. 5.6.30.8 reservedbit 1 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 5.6.30.9 irqa edge pin (irqa edg)bit 0 this bit controls whether the external irqa interrupt is edge- or level-sensitive. during stop and wait modes, it is automatically level-sensitive. ?0 = irqa interrupt is a low-level sensitive (default) ?1 = irqa interrupt is falling-edge sensitive 5.7 resets 5.7.1 reset handshake timing the itcn provides the 56800e core with a reset vector address whenever reset is asserted. the reset vector will be presented until the second rising clock edge after reset is released. 5.7.2 itcn after reset after reset, all of the itcn registers are in their default states. this means all interrupts are disabled except the core irqs with fixed priorities ? illegal instruction ? sw interrupt 3 ? hw stack overflow ? misaligned long word access ? sw interrupt 2 ? sw interrupt 1 ? sw interrupt 0 ? sw interrupt lp these interrupts are enabled at their fixed priority levels.
56f8323 technical data, rev. 11.0 82 freescale semiconductor preliminary part 6 system integration module (sim) 6.1 introduction the sim module is a system catchall for the glue logic that ties together the system-on-chip. it controls distribution of resets and clocks and provides a number of control features. the system integration module is responsible for the following functions: ? reset sequencing ? clock control & distribution ? stop/wait control ? pull-up enables for selected peripherals ? system status registers ? registers for software access to the jtag id of the chip ? enforcing flash security these are discussed in more detail in the sections that follow. 6.2 features the sim has the following features: ? flash security feature prevents unauthorized access to code/data contained in on-chip flash memory ? power-saving clock gating for peripherals ? three power modes (run, wait, stop) to control power utilization stop mode shuts down the 56800e core, system clock, and peripheral clock stop mode entry can optionally disable pll and oscillator (low power vs. fast restart) wait mode shuts down the 56800e core and unnecessary system clock operation run mode supports full part operation ? controls to enable/disable the 56800e core wait and stop instructions ? controls reset sequencing after reset ? software-initiated reset ? four 16-bit registers reset only by a power-on reset usable for general-purpose software control ? system control register ? registers for software access to the jtag id of the chip
operating modes 56f8323 technical data, rev. 11.0 freescale semiconductor 83 preliminary 6.3 operating modes since the sim is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. these are: ? reset mode, which has two submodes: total reset mode C 56800e core and all peripherals are reset core-only reset mode C 56800e core in reset, peripherals are active C this mode is required to provide the on-chip flash interface module time to load data from flash into fm registers. ? run mode the primary mode of operation for this device, in which the 56800e controls chip operation ? debug mode 56800e is controlled via jtag/eonce when in debug mode. all peripherals, except the cop and pwms, continue to run. cop is disabled and pwm outputs are optionally switched off to disable any motor from being driven; see the pwm chapter in the 56f8300 peripheral user manual for details. ? wait mode in wait mode, the core clock and memory clocks are disabled. optionally, the cop can be stopped. similarly, it is an option to switch off pwm outputs to disable any motor from being driven. all other peripherals continue to run. ? stop mode 56800e, memory, and most peripheral clocks are shut down. optionally, the cop and can can be stopped. for lowest power consumption in stop mode, the pll can be shut down. this must be done explicitly before entering stop mode, since there is no automatic mechanism for this. the can (along with any non-gated interrupt) is capable of waking the chip up from stop mode, but is not fully functional in stop mode. 6.4 operating mode register figure 6-1 omr the reset state for mb will depend on the flash secured state. see part 4.2 and part 7 for detailed information on how the operating mode register (omr) ma and mb bits operate in this device. the ex bit is not functional in this device since there is no external memory interface. for all other bits, see the 56f8300 peripheral user manual . note: the omr is not a memory map register; it is directly accessible in code through the acronym omr. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nl cm xp sd r sa ex 0 mb ma type r/w r/w r/w r/w r/w r/w r/w r/w r/w reset 000 0 0 00000000 0x0
56f8323 technical data, rev. 11.0 84 freescale semiconductor preliminary 6.5 register descriptions table 6-1 sim registers (sim_base = $00f350) address offset address acronym register name section location base + $0 sim_control control register 6.5.1 base + $1 sim_rststs reset status register 6.5.2 base + $2 sim_scr0 software control register 0 6.5.3 base + $3 sim_scr1 software control register 1 6.5.3 base + $4 sim_scr2 software control register 2 6.5.3 base + $5 sim_scr3 software control register 3 6.5.3 base + $6 sim_msh_id most significant half of jtag id 6.5.4 base + $7 sim_lsh_id least significant half of jtag id 6.5.5 base + $8 sim_pudr pull-up disable register 6.5.6 reserved base + $a sim_clkosr clko select register 6.5.7 base + $b sim_gps gpio peripheral select register 6.5.7 base + $c sim_pce peripheral clock enable register 6.5.8 base + $d sim_isalh i/o short address location high register 6.5.9 base + $e sim_isall i/o short address location low register 6.5.10
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 85 preliminary figure 6-2 sim register map summary 6.5.1 sim control register (sim_control) figure 6-3 sim control register (sim_control) 6.5.1.1 reservedbits 15C6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. add. offset register name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 $0 sim_ control r 0 0 0 0 0 0 0 0 0 0 once ebl 0 sw rst stop_ disable wait_ disable w $1 sim_ rststs r 0 0 0 0 0 0 0 0 0 0 swr copr extr por 0 0 w $2 sim_scr0 r field w $3 sim_scr1 r field w $4 sim_scr2 r field w $5 sim_scr3 r field w $6 sim_msh_id r 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 w $7 sim_lsh_id r 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 w $8 sim_pudr r 0 0 0 0 reset irq 0 0 0 0 0 0 jtag 0 0 0 w reserved $a sim_ clkosr r 0 0 0 0 0 0 phsa phsb index home clk dis clkosel w $b sim_gps r 0 0 0 0 0 0 0 0 c6 c5 b1 b0 a5 a4 a3 a2 w $c sim_pce r 1 1 adca can 1 dec0 1 tmrc 1 tmra sci1 sci0 spi1 spi0 1 pwma w $d sim_isalh r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 isal[23:22] w $e sim_isall r isal[21:6] w = reserved base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 once ebl 0 sw rst stop_ disable wait_ disable write por 0000000000000000
56f8323 technical data, rev. 11.0 86 freescale semiconductor preliminary 6.5.1.2 once enable (once ebl)bit 5 ? 0 = once clock to 56800e core enabled when core tap is enabled ? 1 = once clock to 56800e core is always enabled 6.5.1.3 software reset (sw rst)bit 4 writing 1 to this field will cause the part to reset. 6.5.1.4 stop disable (stop_disable)bits 3C2 ? 00 = stop mode will be entered when the 56800e core executes a stop instruction ? 01 = the 56800e stop instruction will not cause entry into stop mode; stop_disable can be reprogrammed in the future ? 10 = the 56800e stop instruction will not cause entry into stop mode; stop_disable can then only be changed by resetting the device ? 11 = same operation as 10 6.5.1.5 wait disable (wait_disable)bits 1C0 ? 00 = wait mode will be entered when the 56800e core executes a wait instruction ? 01 = the 56800e wait instruction will not cause entry into wait mode; wait_disable can be reprogrammed in the future ? 10 = the 56800e wait instruction will not cause entry into wait mode; wait_disable can then only be changed by resetting the device ? 11 = same operation as 10 6.5.2 sim reset status register (sim_rststs) bits in this register are set upon any system reset and are initialized only by a power-on reset (por). a reset (other than por) will only set bits in the register; bits are not cleared. only software should clear this register. figure 6-4 sim reset status register (sim_rststs) 6.5.2.1 reservedbits 15C6 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.2.2 software reset (swr)bit 5 when 1, this bit indicates that the previous reset occurred as a result of a software reset (write to sw rst bit in the sim control register). this bit will be cleared by any hardware reset or by software. writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 0 0 swr copr extr por 0 0 write reset 0000000000 00
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 87 preliminary 6.5.2.3 cop reset (copr)bit 4 when 1, the copr bit indicates the computer operating properly (cop) timer-generated reset has occurred. this bit will be cleared by a power-on reset or by software. writing a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it. 6.5.2.4 external reset (extr)bit 3 if 1, the extr bit indicates an external system reset has occurred. this bit will be cleared by a power-on reset or by software. writing a 0 to this bit position will set the bit while writing a 1 to the bit position will clear it. basically, when the extr bit is 1, the previous system reset was caused by the external reset pin being asserted low. 6.5.2.5 power-on reset (por)bit 2 when 1, the por bit indicates a power-on reset occurred some time in the past. this bit can be cleared only by software or by another type of reset. writing a 0 to this bit will set the bit, while writing a 1 to the bit position will clear the bit. in summary, if the bit is 1, the previous system reset was due to a power-on reset. 6.5.2.6 reservedbits 1C0 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.3 sim software control registers (sim_scr0, sim_scr1, sim_scr2, and sim_scr3) only sim scr0 is shown in this section. sim scr1, sim scr2, and sim scr3 are identical in functionality. figure 6-5 sim software control register 0 (sim_scr0) 6.5.3.1 software control data 1 (field)bits 15C0 this register is reset only by the power-on reset (por). it has no part-specific functionality and is intended for use by a software developer to contain data that will be unaffected by the other reset sources (reset pin, software reset, and cop reset). 6.5.4 most significant half of jtag id (sim_msh_id) this read-only register displays the most significant half of the jtag id for the chip. this register reads $01f4. base + $2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read field write reset 0000000000000000
56f8323 technical data, rev. 11.0 88 freescale semiconductor preliminary figure 6-6 most significant half of jtag id (sim_msh_id) 6.5.5 least significant half of jtag id (sim_lsh_id) this read-only register displays the least significant half of the jtag id for the chip. this register reads $001d. figure 6-7 least significant half of jtag id (sim_lsh_id) 6.5.6 sim pull-up disable register (sim_pudr) most of the pins on the chip have on-chip pull-up resistors. pins which can operate as gpio can have these resistors disabled via the gpio function. non-gpio pins can have their pull-ups disabled by setting the appropriate bit in this register. disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not muxed with gpio). each bit in the register (see figure 6-8 ) corresponds to a functional group of pins. see table 2-2 to identify which pins can deactivate the internal pull-up resistor. figure 6-8 sim pull-up disable register (sim_pudr) 6.5.6.1 reservedbits 15C12 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.6.2 reset bit 11 this bit controls the pull-up resistors on the reset pin. base + $6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 write reset 0000000111110100 base + $7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 write reset 0000000000011101 base + $8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 reset irq 0 0 0 0 0 0 jtag 0 0 0 write reset 000 0 000 0 0 0000 0 0 0
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 89 preliminary 6.5.6.3 irqbit 10 this bit controls the pull-up resistors on the irqa pin. 6.5.6.4 reservedbits 9C4 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.6.5 jtagbit 3 this bit controls the pull-up resistors on the trst , tms, and tdi pins. 6.5.6.6 reservedbits 2C0 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.7 clko select register (sim_clkosr) the clko select register can be used to multiplex out any one of the clocks generated inside the clock generation and sim modules. the default value is sys_clk. all other clocks primarily muxed out are for test purposes only, and are subject to significant unspecified latencies at high frequencies. the upper four bits of the gpiob register can function as gpio, quad decoder #0 signals, or as additional clock output signals. gpio has priority and is enabled/disabled via the gpiob_per. if gpiob[7:4] are programmed to operate as peripheral outputs, then the choice between quad decoder #0 and additional clock outputs is made here in the clkosr. the default state is for the peripheral function of gpiob[7:4] to be programmed as quad decoder #0. this can be changed by altering phase0 through index shown in figure 6-9 . the clkout pin is not bonded out in the device. instead, it is offered only as a pad for die-level testing. figure 6-9 clko select register (sim_clkosr) 6.5.7.1 reservedbits 15C10 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.7.2 phasea0 (phsa )bit 9 ? 0 = peripheral output function of gpiob[7] is defined to be phasea0 ? 1 = peripheral output function of gpiob[7] is defined to be the oscillator clock (mstr_osc, see figure 3-4 ) 6.5.7.3 phaseb0 (phsb )bit 8 ? 0 = peripheral output function of gpiob[6] is defined to be phaseb0 ? 1 = peripheral output function of gpiob[6] is defined to be sys_clk2 base + $a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 phsa phsb index home clk dis clkosel write reset 0000000 0 0 0 100000
56f8323 technical data, rev. 11.0 90 freescale semiconductor preliminary 6.5.7.4 index0 (index )bit 7 ? 0 = peripheral output function of gpiob[5] is defined to be index0 ? 1 = peripheral output function of gpiob[5] is defined to be sys_clk 6.5.7.5 home0 (home )bit 6 ? 0 = peripheral output function of gpiob[4] is defined to be home0 ? 1 = peripheral output function of gpiob[4] is defined to be the prescaler clock (fref, see figure 3-4 ) 6.5.7.6 clockout disable (clkdis)bit 5 ? 0 = clkout output is enabled and will output the signal indicated by clkosel ? 1 = clkout is tri-stated 6.5.7.7 clockout select (clkosel)bits 4C0 selects clock to be muxed out on the clko pin. ? 00000 = sys_clk (from rocs - default) ? 00001 = reserved for factory test56800e clock ? 00010 = reserved for factory testxram clock ? 00011 = reserved for factory testpflash odd clock ? 00100 = reserved for factory testpflash even clock ? 00101 = reserved for factory testbflash clock ? 00110 = reserved for factory testdflash clock ? 00111 = mstr_osc oscillator output ? 01000 = f out (from occs) ? 01001 = reserved for factory testipb clock ? 01010 = reserved for factory testfeedback (from occs, this is path to pll) ? 01011 = reserved for factory testprescaler clock (from occs) ? 01100 = reserved for factory testpostscaler clock (from occs) ? 01101 = reserved for factory testsys_clk2 (from occs) ? 01110 = reserved for factory testsys_clk_div2 ? 01111 = reserved for factory testsys_clk_d ? 10000 = adca clock 6.5.8 sim gpio peripheral select register (sim_gps) all of the peripheral pins on the 56f8323 and 56F8123 share their i/o with gpio ports. to select peripheral or gpio control, program the gpiox_per register. when spi 0 and sci 1, quad timer c and sci 0, or pwma and spi 1 are multiplexed, there are two possible peripherals as well as the gpio functionality available for control of the i/o. the sim_gps register is used to determine which peripheral has control. the default peripherals are spi 0, quad timer c, and pwma . note: pwm is not available in the 56F8123 device.
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 91 preliminary as shown in figure 6-10 , the gpio has the final control over the pin function. sim_gps simply decides which peripheral will be routed to the i/o. figure 6-10 overall control of pads using sim_gps control figure 6-11 gpio peripheral select register (sim_gps) 6.5.8.1 reservedbits 15C8 this bit field is reserved or not implemented. it is read as 0 and cannot be modified by writing. 6.5.8.2 gpioc6 (c6)bit 7 this bit selects the alternate function for gpioc6. ? 0 = tc0 (default) ? 1 = txd0 6.5.8.3 gpioc5 (c5)bit 6 this bit selects the alternate function for gpioc5. ? 0 = tc1 (default) ? 1 = rxd0 base + $b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 0 c6 c5 b1 b0 a5 a4 a3 a2 write reset 0000000000 0 0 0 0 0 0 gpiox_per register gpio controlled i/o pad control sim_gps register quad timer controlled sci controlled 0 1 0 1
56f8323 technical data, rev. 11.0 92 freescale semiconductor preliminary 6.5.8.4 gpiob1 (b1)bit 5 this bit selects the alternate function for gpiob1. ? 0 = miso0 (default) ? 1 = rxd1 6.5.8.5 gpiob0 (b0)bit 4 this bit selects the alternate function for gpiob0. ? 0 = ss0 (default) ? 1 = txd1 6.5.8.6 gpioa5 (a5)bit 3 this bit selects the alternate function for gpioa5. ?0 = pwma5 ? 1 = sclk1 6.5.8.7 gpioa4 (a4)bit 2 this bit selects the alternate function for gpioa4. ?0 = pwma4 ?1 = mos1 6.5.8.8 gpioa3 (a3)bit 1 this bit selects the alternate function for gpioa3. ?0 = pwma3 ?1 = miso1 6.5.8.9 gpioa2 (a2)bit 0 this bit selects the alternate function for gpioa2. ?0 = pwma2 ? 1 = ss1 6.5.9 peripheral clock enable register (sim_pce) the peripheral clock enable register is used to enable or disable clocks to the peripherals as a power savings feature. the clocks can be individually controlled for each peripheral on the chip. figure 6-12 peripheral clock enable register (sim_pce) base + $c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 adca can 1 dec0 1 tmrc 1 tmra sci 1 sci 0 spi1 spi0 1 pwma write reset 1111111111111 111
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 93 preliminary 6.5.9.1 reservedbits 15C14 this bit field is reserved or not implemented. it is read as 1 and cannot be modified by writing. 6.5.9.2 analog-to-digital converter a enable (adca)bit 13 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.3 flexcan enable (can)bit 12 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.4 reservedbit 11 this bit field is reserved or not implemented. it is read as 1 and cannot be modified by writing. 6.5.9.5 decoder 0 enable (dec0)bit 10 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.6 reservedbit 9 this bit field is reserved or not implemented. it is read as 1 and cannot be modified by writing. 6.5.9.7 quad timer c enable (tmrc)bit 8 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.8 reservedbit 7 this bit field is reserved or not implemented. it is read as 1 and cannot be modified by writing. 6.5.9.9 quad timer a enable (tmra)bit 6 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled)
56f8323 technical data, rev. 11.0 94 freescale semiconductor preliminary 6.5.9.10 serial communications interface 1 enable (sci1)bit 5 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.11 serial communications interface 0 enable (sci0)bit 4 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.12 serial peripheral interface 1 enable (spi1)bit 3 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.13 serial peripheral interface 0 enable (spi0)bit 2 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 reservedbit 1 this bit field is reserved or not implemented. it is read as 1 and cannot be modified by writing. 6.5.9.15 pulse width modulator a enable (pwma)bit 0 each bit controls clocks to the indicated peripheral. ? 1 = clocks are enabled ? 0 = the clock is not provided to the peripheral (the peripheral is disabled) 6.5.10 i/o short address location register (sim_isalh and sim_isall) the i/o short address location registers are used to specify the memory referenced via the i/o short address mode. the i/o short address mode allows the instruction to specify the lower six bits of address; the upper address bits are not directly controllable. this register set allows limited control of the full address, as shown in figure 6-13 . note: if this register is set ot something other than the top of memory (eonce register space) and the ex bit in the omr is set to 1, the jtag port cannot access the on-chip eonce registers, and debug functions will be affected.
register descriptions 56f8323 technical data, rev. 11.0 freescale semiconductor 95 preliminary figure 6-13 i/o short address determination with this register set, an interrupt driver can set the sim_isall register pair to point to its peripheral registers and then use the i/o short addressing mode to reference them. the isr should restore this register to its previous contents prior to returning from interrupt. note: the default value of this register set points to the eonce registers. note: the pipeline delay between setting this register set and using short i/o addressing with the new value is five cycles. figure 6-14 i/o short address location high register (sim_isalh) 6.5.10.1 input/output short address low (isal[23:22])bit 1C0 this field represents the upper two address bits of the hard coded i/o short address. figure 6-15 i/o short address location low register (sim_isall) base + $d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read 1 1 1 1 1 1 1 1 1 1 1 1 1 1 isal[23:22] write reset 111111 1 1 1111 1 1 11 base + $e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read isal[21:6] write reset 111111 1 1 1111 1 1 11 instruction portion hard coded address portion 6 bits from i/o short address mode instruction 16 bits from sim_isall register 2 bits from sim_isalh register full 24-bit for short i/o address
56f8323 technical data, rev. 11.0 96 freescale semiconductor preliminary 6.5.10.2 input/output short address low (isal[21:6])bit 15C0 this field represents the lower 16 address bits of the hard coded i/o short address. 6.6 clock generation overview the sim uses an internal master clock from the occs (clkgen) module to produce the peripheral and system (core and memory) clocks. the maximum master clock frequency is 120mhz. peripheral and system clocks are generated at half the master clock frequency and therefore at a maximum 60mhz. the sim provides power modes (stop, wait) and clock enables (sim_pce register, clk_dis, once_ebl) to control which clocks are in operation. the occs, power modes, and clock enables provide a flexible means to manage power consumption. power utilization can be minimized in several ways. in the occs, the relaxation oscillator, crystal oscillator, and pll may be shut down when not in use. when the pll is in use, its prescaler and postscaler can be used to limit pll and master clock frequency. power modes permit system and/or peripheral clocks to be disabled when unused. clock enables provide the means to disable individual clocks. some peripherals provide further controls to disable unused subfunctions. refer to part 3 on-chip clock synthesis (occs) , and the 56f8300 peripheral user manual for further details. the memory, peripheral and core clocks all operate at the same frequency (60mhz max). 6.7 power-down modes the 56f8323/56F8123 operate in one of three power-down modes, as shown in table 6-2 . all peripherals, except the cop/watchdog timer, run off the ipbus clock frequency, which is the same as the main processor frequency in this architecture. the maximum frequency of operation is sys_clk = 60mhz. refer to the pce register in part 6.5.9 and adc power modes. power is a function of the system frequency, which can be controlled through the occs. table 6-2 clock operation in power-down modes mode core clocks peripheral clocks description run active active device is fully functional wait core and memory clocks disabled active peripherals are active and can produce interrupts if they have not been masked off. interrupts will cause the core to come out of its suspended state and resume normal operation. typically used for power-conscious applications. stop system clocks continue to be generated in the sim, but most are gated prior to reaching memory, core and peripherals. the only possible recoveries from stop mode are: 1. can traffic (1st message will be lost) 2. non-clocked interrupts (irqa ) 3. cop reset 4. external reset 5. power-on reset
stop and wait mode disable function 56f8323 technical data, rev. 11.0 freescale semiconductor 97 preliminary 6.8 stop and wait mode disable function figure 6-16 internal stop disable circuit the 56800e core contains both stop and wait instructions. both put the cpu to sleep. for lowest power consumption in stop mode, the pll can be shut down. this must be done explicitly before entering stop mode, since there is no automatic mechanism for this. when the pll is shut down, the 56800e system clock must be set equal to the prescaler output. some applications require the 56800e stop and wait instructions be disabled. to disable those instructions, write to the sim control register (sim_control) described in part 6.5.1 . this procedure can be on either a permanent or temporary basis. permanently assigned applications last only until their next reset. 6.9 resets the sim supports four sources of reset. the two asynchronous sources are the external reset pin and the power-on reset (por). the two synchronous sources are the software reset, which is generated within the sim itself, by writing to the sim_control register, and the cop reset. reset begins with the assertion of any of the reset sources. release of reset to various blocks is sequenced to permit proper operation of the device. a por reset is declared when reset is removed and any of the three voltage detectors (1.8v por, 2.2v core voltage, or 2.7v i/o voltage) indicate a low supply voltage condition. por will continue to be asserted until all voltage detectors indicate a stable supply is available (note that as power is removed por is not declared until the 1.8v core voltage threshold is reached.) a por reset is then extended for 64 clock cycles to permit stabilization of the clock source, followed by a 32 clock window in which sim clocking is initiated. it is then followed by a 32 clock window in which peripherals are released to implement flash security, and, finally, followed by a 32 clock window in which the core is initialized. after completion of the described reset sequence, application code will begin execution. resets may be asserted asynchronously, but are always released internally on a rising edge of the system clock. d-flop dq c d-flop d q c r 56800e stop_dis permanent disable reprogrammable disable clock select reset d note: wait disable circuit is similar
56f8323 technical data, rev. 11.0 98 freescale semiconductor preliminary part 7 security features the 56f8323/56F8123 offer security features intended to prevent unauthorized users from reading the contents of the flash memory (fm) array. the flash security consists of several hardware interlocks that block the means by which an unauthorized user could gain access to the flash array. however, part of the security must lie with the users code. an extreme example would be users code that dumps the contents of the internal program, as this code would defeat the purpose of security. at the same time, the user may also wish to put a backdoor in his program. as an example, the user downloads a security key through the sci, allowing access to a programming routine that updates parameters stored in another section of the flash. 7.1 operation with security enabled once the user has programmed the flash with his application code, the device can be secured by programming the security bytes located in the fm configuration field, which occupies a portion of the fm array. these non-volatile bytes will keep the part secured through reset and through power-down of the device. only two bytes within this field are used to enable or disable security. refer to the flash memory section in the 56f8300 peripheral user manual for the state of the security bytes and the resulting state of security. when flash security mode is enabled in accordance with the method described in the flash memory module specification, the device will disable the eonce interface, preventing access to internal code. normal program execurtion is otherwise unaffected. 7.2 flash access blocking mechanisms the 56f8323/56F8123 have several operating functional and test modes. effective flash security must address operating mode selection and anticipate modes in which the on-chip flash can be compromised and read without explicit user permission. methods to block these are outlined in the next subsections. 7.2.1 forced operating mode selection at boot time, the sim determines in which functional modes the device will operate. these are: ? unsecured mode ? secure mode (eonce disabled) when flash security is enabled as described in the flash memory module specification, the device will disable the eonce debug interface. 7.2.2 disabling eonce access on-chip flash can be read by issuing commands across the eonce port, which is the debug interface for the 56800e core. the trst , tclk, tms, tdo, and tdi pins comprise a jtag interface onto which the eonce port functionality is mapped. when the device boots, the chip-level jtag tap (test access port) is active and provides the chips boundary scan capability and access to the id register.
flash access blocking mechanisms 56f8323 technical data, rev. 11.0 freescale semiconductor 99 preliminary proper implementation of flash security requires that no access to the eonce port is provided when security is enabled. the 56800e core has an input which disables reading of internal memory via the jtag/eonce. the fm sets this input at reset to a value determined by the contents of the fm security bytes. 7.2.3 flash lockout recovery if a user inadvertently enables flash security on the device, a built-in lockout recovery mechanism can be used to reenable access to the device. this mechanism completely reases all on-chip flash, thus disabling flash security. access to this recovery mechanism is built into codewarrior via an instruction in memory configuration ( .cfg ) files. add, or uncomment the following configuration command: unlock_flash_on_connect 1 for more information, please see codewarrior mc56f83xx/dsp5685x family targeting manual . the lockout_recovery instruction has an associated 7-bit data register (dr) that is used to control the clock divider circuit within the fm module. this divider, fm_clkdiv[6:0], is used to control the period of the clock used for timed events in the fm erase algorithm. this register must be set with appropriate values before the lockout sequence can begin. refer to the 56f8300 peripheral user manual for more details on setting this register value. the value of the jtag fm_clkdiv[6:0] will replace the value of the fm register fmclkd that divides down the system clock for timed events, as illustrated in figure 7-1 . fm_clkdiv[6] will map to the prdiv8 bit, and fm_clkdiv[5:0] will map to the div[5:0] bits. the combination of prdiv8 and div must divide the fm input clock down to a frequency of 150khz-200khz. the writing the fmclkd register section in the flash memory chapter of the 56f8300 peripheral user manual gives specific equations for calculating the correct values. figure 7-1 jtag to fm connection for lockout recovery two examples of fm_clkdiv calculations follow. sys_clk jtag fmclkd divider 7 7 7 2 fmclkdiv fmerase flash memory clock input
56f8323 technical data, rev. 11.0 100 freescale semiconductor preliminary example 1: if the system clock is the 8mhz crystal frequency because the pll has not been set up, the input clock will be below 12.8mhz, so prdiv8=fm_clkdiv[6]=0. using the following equation yields a div value of 19 for a clock of 200khz, and a div value of 20 for a clock of 190khz. this translates into an fm_clkdiv[6:0] value of $13 or $14, respectively. example 2: in this example, the system clock has been set up with a value of 32mhz, making the fm input clock 16mhz. because that is greater than 12.8mhz, prdiv8=fm_clkdiv[6]=1. using the following equation yields a div value of 9 for a clock of 200khz, and a div value of 10 for a clock of 181khz. this translates to an fm_clkdiv[6:0] value of $49 or $4a, respectively. once the lockout_recovery instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. after the data register has been updated, the user must transition the tap controller into the run-test/idle state for the lockout sequence to commence. the controller must remain in this state until the erase sequence has completed. for details, see the jtag section in the 56f8300 peripheral user manual . note: once the lockout recovery sequence has completed, the user must reset both the jtag tap controller (by asserting trst ) and the device (by asserting external chip reset) to return to normal unsecured operation. 7.2.4 product analysis the recommended method of unsecuring a programmed device for product analysis of field failures is via the backdoor key access. the customer would need to supply technical support with the backdoor key and the protocol to access the backdoor routine in the flash. additionally, the keyen bit that allows backdoor key access must be set. an alternative method for performing analysis on a secured microcontroller would be to mass-erase and reprogram the flash with the original code, but to modify the security bytes. to insure that a customer does not inadvertently lock himself out of the device during programming, it is recommended that he program the backdoor access key first, his application code second and the security bytes within the fm configuration field last. sys_clk (2) ) ( < < (div + 1) 150[khz] 200[khz] sys_clk (2)(8) ) ( < < (div + 1) 150[khz] 200[khz]
introduction 56f8323 technical data, rev. 11.0 freescale semiconductor 101 preliminary part 8 general purpose input/output (gpio) 8.1 introduction this section is intended to supplement the gpio information found in the 56f8300 peripheral user manual and contains only chip-specific information. this information supercedes the generic information in the 56f8300 peripheral user manual . 8.2 configuration there are three gpio ports defined on the 56f8323/56F8123. the width of each port and the associated peripheral function is shown in table 8-1 and table 8-2 . the specific mapping of gpio port pins is shown in table 8-3 . note: pins in italics are not available in the 56F8123 device. table 8-1 56f8323 gpio ports configuration gpio port port width available pins in 56f8323 peripheral function reset function a12 12 pwm, spi 1 pwm b8 8 spi 0, dec 0, tmra, sci 1 spi 0, dec 0 c7 7 xtal, extal, can, tmrc, sci 0 xtal, extal, can, tmrc table 8-2 56F8123 gpio ports configuration gpio port port width available pins in 56F8123 peripheral function reset function a12 12 spi 1 must be reconfigured b8 8 spi 0, sci 1, tmra spi 0; other pins must be reconfigured c7 7 xtal, extal, tmrc, sci 0 xtal, extal, tmrc; other pins must be reconfigured
56f8323 technical data, rev. 11.0 102 freescale semiconductor preliminary table 8-3 gpio external signals map gpio function peripheral function package pin notes gpioa0 pwma0 3 pwm is not available in 56F8123 gpioa1 pwma1 4 pwm is not available in 56F8123 gpioa2 pwma2 / ssi 7 sim register sim_gps is used to select between spi1 and pwma on a pin-by-pin basis pwm is not available in 56F8123 gpioa3 pwma3 / miso1 8 sim register sim_gps is used to select between spi1 and pwma on a pin-by-pin basis pwm is not available in 56F8123 gpioa4 pwma4 / mosi1 9 sim register sim_gps is used to select between spi1 and pwma on a pin-by-pin basis pwm is not available in 56F8123 gpioa5 pwma5 / sclk1 10 sim register sim_gps is used to select between spi1 and pwma on a pin-by-pin basis pwm is not available in 56F8123 gpioa6 faulta0 13 gpioa7 faulta1 14 gpioa8 faulta2 15 gpioa9 isa0 16 gpioa10 isa0 18 gpioa11 isa2 19 gpiob0 ss0 / txd1 21 sim register sim_gps is used to select between spi1 and pwma on a pin-by-pin basis gpiob1 miso0 / rxd1 22 sim register sim_gps is used to select between spi1 and pwma on a pin-by-pin basis gpiob2 mosi0 24 gpiob3 sclk0 25 gpiob4 home0 / ta3 49 quad decoder 0 register deccr is used to select between decoder 0 and timer a quad decoder is not available in 56F8123 gpiob5 index0 / ta2 50 quad decoder 0 register deccr is used to select between decoder 0 and timer a quad decoder is not available in 56F8123 gpiob6 phaseb0 / ta1 51 quad decoder 0 register deccr is used to select between decoder 0 and timer a quad decoder is not available in 56F8123
memory maps 56f8323 technical data, rev. 11.0 freescale semiconductor 103 preliminary 8.3 memory maps the width of the gpio port defines how many bits are implemented in each of the gpio registers. based on this and the default function of each of the gpio pins, the reset values of the gpiox_pur and gpiox_per registers change from port to port. tables 4-21 through 4-23 define the actual reset values of these registers. part 9 joint test action group (jtag) 9.1 jtag information please contact your freescale sales representative or authorized distributor for device/package-specific bsdl information. gpiob7 phasea0 / ta0 52 quad decoder 0 register deccr is used to select between decoder 0 and timer a quad decoder is not available in 56F8123 gpioc0 extal 46 pull-ups default to disabled gpioc1 xtal 47 pull-ups default to disabled gpioc2 can_rx 61 can is not available in 56F8123 gpioc3 can_tx 62 can is not available in 56F8123 gpioc4 tc3 63 gpioc5 tc1 / rxd0 64 sim register sim_gps is used to select between timer c and sci0 on a pin-by-pin basis gpioc6 tc0 / txd0 1 sim register sim_gps is used to select between timer c and sci0 on a pin-by-pin basis table 8-3 gpio external signals map (continued) gpio function peripheral function package pin notes
56f8323 technical data, rev. 11.0 104 freescale semiconductor preliminary part 10 specifications 10.1 general characteristics the 56f8323/56F8123 are fabricated in high-density cmos with 5v-tolerant ttl-compatible digital inputs. the term 5v-tolerant refers to the capability of an i/o pin, built on a 3.3v-compatible process technology, to withstand a voltage up to 5.5v without damaging the device. many systems have a mixture of devices designed for 3.3v and 5v power supplies. in such systems, a bus may carry both 3.3v- and 5v-compatible i/o voltage levels (a standard 3.3v i/o is designed to receive a maximum voltage of 3.3v 10% during normal operation without causing damage). this 5v-tolerant capability therefore offers the power savings of 3.3v i/o levels combined with the ability to receive 5v levels without damage. absolute maximum ratings in table 10-1 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. note: all specifications meet both automotive and industrial requirements unless individual specifications are listed. note: the 56F8123 device is guaranteed to 40mhz and specified to meet industrial requirements only. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
general characteristics 56f8323 technical data, rev. 11.0 freescale semiconductor 105 preliminary note: the 56F8123 device is specified to meet industrial requirements only; pwm, can and quad decoder are not available on the 56F8123 device. note: the overall life of this device may be reduced if subjected to extended use over 110c junction. for additional information, please contact your sales representative. note: pins in italics are not available in the 56F8123 device. pin group 1: tc0-1, tc3, faulta0-2 , isa0-2 , ss0 , miso0, mosi0, sclk0, home0 , index0 , phasea0 , phaseb0 , can_rx , can_tx , gpioc0-1 pin group 2: tdo pin group 3: pwma0-5 pin group 4: reset , tms, tdi, trst , irqa pin group 5: tck pin group 6: xtal, extal pin group 7: ana0-7 pin group 8: ocr_dis table 10-1 absolute maximum ratings (v ss = v ssa_adc = 0) characteristic symbol notes min max unit supply voltage v dd_io - 0.3 4.0 v adc supply voltage v dda_adc, v refh v refh must be less than or equal to v dda_adc - 0.3 4.0 v oscillator / pll supply voltage v dda_osc_pll - 0.3 4.0 v internal logic core supply voltage v dd_core ocr_dis is high - 0.3 3.0 v input voltage (digital) v in pin groups 1, 3, 4, 5 -0.3 6.0 v input voltage (analog) v ina pin groups 7, 8 -0.3 4.0 v output voltage v out pin groups 1, 2, 3 -0.3 4.0 v output voltage (open drain) v outod gpio pins used in open drain mode -0.3 6.0 v ambient temperature (automotive) t a -40 125 c ambient temperature (industrial) t a -40 105 c junction temperature (automotive) t j -40 150 c junction temperature (industrial) t j -40 125 c storage temperature (automotive) t stg -55 150 c storage temperature (industrial) t stg -55 150 c
56f8323 technical data, rev. 11.0 106 freescale semiconductor preliminary 1. theta-ja determined on 2s2p test boards is frequently lower than would be observed in an application. determined on 2s2p the r- mal test board. 2. junction-to-ambient thermal resistance, theta-ja (r ja ), was simulated to be equivalent to the jedec specification jesd51-2 in a horizontal configuration in natural convection. theta-ja was also simulated on a thermal test board with two internal plan es (2s2p, where s is the number of signal layers and p is the number of planes) per jesd51-6 and jesd51-7. the correct name for theta-ja for forced convection or with the non-single layer boards is theta-jma. 3. junction-to-case thermal resistance, theta-jc (r jc ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. the basic cold plate measurement technique is described by mil-std 883d, method 1012.1. this is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 4. thermal characterization parameter, psi-jt ( jt ), is the "resistance" from junction to reference point thermocouple on top cen- ter of case as defined in jesd51-2. jt is a useful value to estimate junction temperature in steady-state customer environ- ments. 5. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperatu re, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. see part 12.1 for more details on thermal design considerations. table 10-2 56f8323/56F8123 electrostatic discharge (esd) protection characteristic min typ max unit esd for human body model (hbm) 2000 v esd for machine model (mm) 200 v esd for change device model (cdm) 500 v table 10-3 thermal characteristics 6 characteristic comments symbol value unit notes 64-pin lqfp junction to ambient natural convection r ja 41 c/w 2 junction to ambient (@1m/sec) r jma 34 c/w 2 junction to ambient natural convection four layer board (2s2p) r jma (2s2p) 34 c/w 1,2 junction to ambient (@1m/sec) four layer board (2s2p) r jma 29 c/w 1,2 junction to case r jc 8c/w3 junction to center of case jt 2 c/w 4, 5 i/o pin power dissipation p i/o user-determined w power dissipation p d p d = (i dd x v dd + p i/o ) w maximum allowed p d p dmax (tj - ta) / ja c
general characteristics 56f8323 technical data, rev. 11.0 freescale semiconductor 107 preliminary note: the 56F8123 device is guaranteed to 40mhz and specified to meet industrial requirements only; pwm, can and quad decoder are not available on the 56F8123 device. note: total chip source or sink current cannot exceed 150ma. note: pins in italics are not available in the 56F8123 device. see pin groups in table 10-1 table 10-4 recommended operating conditions (v reflo = 0v, v ss = v ssa_adc = 0v , v dda = v dda_adc = v dda_osc_pll ) characteristic symbol notes min typ max unit supply voltage v dd_io 33.33.6 v adc supply voltage v dda_adc, v refh v refh must be less than or equal to v dda_adc 33.33.6 v oscillator / pll supply voltage v dda_osc_pll 33.33.6 v internal logic core supply voltage v dd_core ocr_dis is high 2.25 2.5 2.75 v device clock frequency fsysclk 060/40 mhz input high voltage (digital) v in pin groups 1, 3, 4, 5 25.5 v input high voltage (analog) v iha pin group 8 2v dda +0.3 v input high voltage (xtal/extal, xtal is not driven by an external clock) v ihc pin group 6 v dda -0.8 v dda +0.3 v input high voltage (xtal/extal, xtal is driven by an external clock) v ihc pin group 6 2v dda +0.3 v input low voltage v il pin groups 1, 3, 4, 5, 6, 8 -0.3 0.8 v output high source current v oh = 2.4v (v oh min.) i oh pin groups 1, 2 -4 ma pin group 3 -12 output low sink current v ol = 0.4v (v ol max) i ol pin groups 1, 2 4 ma pin group 3 12 ambient operating temperature (automotive) t a -40 125 - (r ja x p d ) c ambient operating temperature (industrial) t a -40 105 - (r ja x p d ) c flash endurance (automotive) (program erase cycles) n f t a = -40c to 125c 10,000 cycles flash endurance (industrial) (program erase cycles) n f t a = -40c to 105c 10,000 cycles flash data retention (automotive and industrial) t r t j <= 70c avg 15 years
56f8323 technical data, rev. 11.0 108 freescale semiconductor preliminary 10.2 dc electrical characteristics note: the 56F8123 device is specified to meet industrial requirements only; pwm, can and quad decoder are not available on the 56F8123 device. see pin groups in table 10-1 table 10-5 dc electrical characteristics at recommended operating conditions; see table 10-4 characteristic symbol notes min typ max unit test conditions output high voltage v oh 2.4 vi oh = i ohmax output low voltage v ol 0.4 vi ol = i olmax digital input current high pull-up enabled or disabled i ih pin groups 1, 3, 4 0+/- 2.5 av in = 3.0v to 5.5v digital input current high with pull-down i ih pin group 5 40 80 160 av in = 3.0v to 5.5v analog input current high i iha pin group 8 0+/- 2.5 av in = v dda adc input current high i ihadc pin group 7 0+/- 3.5 av in = v dda digital input current low pull-up enabled i il pin groups 1, 3, 4 -200 -100 -50 av in = 0v digital input current low pull-up disabled i il pin groups 1, 3, 4 0+/- 2.5 av in = 0v digital input current low with pull-down i il pin group 5 0+/- 2.5 av in = 0v analog input current low i ila pin group 8 0+/- 2.5 av in = 0v adc input current low i iladc pin group 7 0+/- 3.5 av in = 0v extal input current low clock input i extal 0+/- 2.5 av in = v dda or 0v xtal input current low clock input i xtal clkmode = high 0+/- 2.5 av in = v dda or 0v clkmode = low 200 av in = v dda or 0v output current high impedance state i oz pin groups 1, 2, 3 0+/- 2.5 av out = 3.0v to 5.5v or 0v schmitt trigger input hysteresis v hys pin groups 1, 3, 4, 5 0.3 v input capacitance (extal/xtal) c inc 4.5 pf output capacitance (extal/xtal) c outc 5.5 pf input capacitance c in 6 pf output capacitance c out 6 pf
dc electrical characteristics 56f8323 technical data, rev. 11.0 freescale semiconductor 109 preliminary table 10-6 power-on reset low voltage parameters characteristic symbol min typ max units por trip point rising 1 1. both v ei2.5 and v ei3.3 thresholds must be met for por to be released on power-up. por r v por trip point falling por f 1.75 1.8 1.9 v lvi, 2.5v supply, trip point 2 2. when v dd_core drops below v ei2.5 , an interrupt is generated. v ei2.5 2.14 v lvi, 3.3v supply, trip point 3 3. when v dd_core drops below v ei3.3 , an interrupt is generated. v ei3.3 2.7 v bias current i bias 110 130 a table 10-7 current consumption per power supply pin (typical) on-chip regulator enabled (ocr_dis = low) mode i dd_io 1 1. no output switching (output switching current can be estimated from i = cvf for each output) 2. includes processor core current supplied by internal voltage regulator i dd_adc i dd_osc_pll test conditions run1_mac 115ma 25ma 2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? continuous mac instructions with fetches from data ram ? adc powered on and clocked wait3 60ma 35 a2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? adc powered off stop1 5.7ma 0 a 360 a ? 4mhz device clock ? all peripheral clocks are off ? relaxation oscillator is on ? adc powered off ? pll powered off stop2 5ma 0 a 145 a ? relaxation oscillator is off ? all peripheral clocks are off ? adc powered off ? pll powered off
56f8323 technical data, rev. 11.0 110 freescale semiconductor preliminary 10.2.1 voltage regulator specifications the 56f8323/56F8123 have two on-chip regulators. one supplies the pll and has no external pins; therefore, it has no external characteristics which must be guaranteed (other than proper operation of the device). the second regulator supplies approximately 2.6v to the devices core logic. this regulator requires two external 2.2 f, or greater, capacitors for proper operation. ceramic and tantalum capacitors tend to provide better performance tolerances. the output voltage can be measured directly on the v cap pins. the specifications for this regulator are shown in table 10-9 . table 10-8 current consumption per power supply pin (typical) on-chip regulator disabled (ocr_dis = high) mode i dd_core i dd_io 1 1. no output switching (output switching current can be estimated from i = cvf for each output) i dd_adc i dd_osc_pll test conditions run1_mac 110ma 13 a25ma 2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? continuous mac instructions with fetches from data ram ? adc powered on and clocked wait3 55ma 13 a35 a2.5ma ? 60mhz device clock ? all peripheral clocks are enabled ? adc powered off stop1 700 a13 a0 a360 a ? 4mhz device clock ? all peripheral clocks are off ? relaxation oscillator is on ? adc powered off ? pll powered off stop2 100 a13 a0 a145 a ? relaxation oscillator is off ? all peripheral clocks are off ? adc powered off ? pll powered off
dc electrical characteristics 56f8323 technical data, rev. 11.0 freescale semiconductor 111 preliminary table 10-9. regulator parameters characteristic symbol min typical max unit unloaded output voltage (0ma load) v rnl 2.25 2.75 v loaded output voltage (200ma load) v rl 2.25 2.75 v line regulation @ 250ma load (v dd 33 ranges from 3.0v to 3.6v) v r 2.25 2.75 v short circuit current (output shorted to ground) iss 700 ma bias current i bias 5.87 ma power-down current i pd 0 2 a short-circuit tolerance (output shorted to ground) t rsc 30minutes table 10-10. pll parameters characteristics symbol min typical max unit pll start-up time t ps 0.3 0.5 10 ms resonator start-up time t rs 0.1 0.18 1 ms min-max period variation t pv 120 200 ps peak-to-peak jitter t pj 175 ps bias current i bias 1.52 ma quiescent current, power-down mode i pd 100 150 a
56f8323 technical data, rev. 11.0 112 freescale semiconductor preliminary 10.2.2 temperature sense note: temperature sensor is not available in the 56F8123 device. 10.3 ac electrical characteristics tests are conducted using the input levels specified in table 10-5 . unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in figure 10-1 . table 10-11 temperature sense parametrics characteristics symbol min typical max unit slope (gain) 1 m 7.762 mv/c room trim temp. 1, 2 1. includes the adc conversion of the analog temperature sense voltage. 2. the adc is not calibrated for the conversion of the temperature sensor trim value stored in the flash memory at fmopt0 and fmopt1. t rt 24 26 28 c hot trim temp. (industrial) 1,2 t ht 122 125 128 c hot trim temp. (automotive) 1,2 t ht 147 150 153 c output voltage @ v dda_adc = 3.3v, t j =0c 1 v ts0 1.370 v supply voltage v dda_adc 3.0 3.3 3.6 v supply current - off i dd-off 10 a supply current - on i dd-on 250 a accuracy 3,1 from -40c to 150c using v ts = mt + v ts0 3. see application note, an1980, for methods to increase accuracy. t acc -6.7 0 6.7 c resolution 4, 5,1 4. assuming a 12-bit range from 0v to 3.3v. 5. typical resolution calculated using equation, r es = (v refh - v reflo ) x 1 2 12 m r es 0.104 c / bit
flash memory characteristics 56f8323 technical data, rev. 11.0 freescale semiconductor 113 preliminary figure 10-1 input signal measurement references figure 10-2 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh figure 10-2 signal states 10.4 flash memory characteristics table 10-12 flash timing parameters characteristic symbol min typ max unit program time 1 1. there is additional overhead which is part of the programming sequence. see the 56f8300 peripheral user manual for details. program time is per 16-bit word in flash memory. two words at a time can be programmed within the pro- gram flash module, as it contains two interleaved memories. t prog 20 s erase time 2 2. specifies page erase time. there are 512 bytes per page in the data and boot flash memories. the program flash module uses two interleaved flash memories, increasing the effective page size to 1024 bytes. t erase 20 ms mass erase time t me 100 ms v ih v il fall time input signal note: the midpoint is v il + (v ih C v il )/2. midpoint1 low high 90% 50% 10% rise time data invalid state data1 data2 valid data tri-stated data3 valid data2 data3 data1 valid data active data active
56f8323 technical data, rev. 11.0 114 freescale semiconductor preliminary 10.5 external clock operation timing figure 10-3 external clock timing table 10-13 external clock operation timing requirements 1 1. parameters listed are guaranteed by design. characteristic symbol min typ max unit frequency of operation (external clock driver) 2 56f8323 2. see figure 10-3 for details on using the recommended connection of an external clock driver. f osc 0120mhz frequency of operation (external clock driver) 2 56F8123 f osc 080mhz clock pulse width 3 3. the high or low pulse width must be no smaller than 8.0ns or the chip will not function. t pw 3.0 ns external clock input rise time 4 4. external clock input rise time is measured from 10% to 90% t rise 15ns external clock input fall time 5 5. external clock input fall time is measured from 90% to 10% t fall 15ns external clock v ih v il note: the midpoint is v il + (v ih C v il )/2. 90% 50% 10% 90% 50% 10% t pw t pw t fall t rise
phase locked loop timing 56f8323 technical data, rev. 11.0 freescale semiconductor 115 preliminary 10.6 phase locked loop timing 10.7 crystal oscillator parameters table 10-14 pll timing characteristic symbol min typ max unit external reference crystal frequency for the pll 1 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8mhz input crystal. f osc 488mhz pll output frequency 2 (f out )56f8323 2. zclk may not exceed 60mhz. for additional information on zclk and (f out /2), please refer to the occs chapter in the 56f8300 peripheral user manual . f op 160 260 mhz pll output frequency 2 (f out )56F8123 f op 160 160 mhz pll stabilization time 3 -40 to +125 c 3. this is the minimum time required after the pll set up is changed to ensure reliable operation. t plls 110ms table 10-15 crystal oscillator parameters characteristic symbol min typ max unit crystal start-up time t cs 4510ms resonator start-up time t rs 0.1 0.18 1 ms crystal esr r esr 120 ohms crystal peak-to-peak jitter t d 70 250 ps crystal min-max period variation t pv 0.12 1.5 ns resonator peak-to-peak jitter t rj 300 ps resonator min-max period variation t rp 300 ps bias current, high-drive mode i biash 250 290 a bias current, low-drive mode i biasl 80 110 a quiescent current, power-down mode i pd 0 1 a
56f8323 technical data, rev. 11.0 116 freescale semiconductor preliminary note: an lsb change in the tuning code results in an 82ps shift in the frequency period, while an msb change in the tuning code results in a 41ns shift in the frequency period. figure 10-4 frequency versus temperature table 10-16 relaxation oscillator parameters characteristic min typ max units center frequency 8 mhz minimum tuning step size (see note) 82ps maximum tuning step size (see note) 41ns frequency accuracy -50 c to +150 c (see figure 10-4 ) +/- 1.78 +/- 2.0 % maximum cycle-to-cycle jitter 500ps stabilization time from power-up 4 s frequency in mhz temperature - 50 - 30 - 10 + 10 + 30 + 50 + 70 + 90 + 110 + 130 + 150 7.5 7.6 7.7 7.9 7.8 8.0 8.1 8.2 typical response
reset, stop, wait, mode select, and interrupt timing 56f8323 technical data, rev. 11.0 freescale semiconductor 117 preliminary 10.8 reset, stop, wait, mode select, and interrupt timing note: all address and data buses described here are internal. figure 10-5 asynchronous reset timing figure 10-6 external interrupt timing (negative edge-sensitive) table 10-17 reset, stop, wait, mode select, and interrupt timing 1,2 1. in the formulas, t = clock cycle. for an operating frequency of 60mhz, t = 16.67ns. at 8mhz (used during reset and stop modes), t = 125ns. 2. parameters listed are guaranteed by design. characteristic symbol typical min typical max unit see figure minimum reset assertion duration t ra 16t ns 10-5 edge-sensitive interrupt request width t irw 1.5t ns 10-6 irqa , irqb assertion to general purpose output valid, caused by first instruction execution in the interrupt service routine t ig 18t ns 10-7 t ig - fast 14t irqa width assertion to recover from stop state 3 3. the interrupt instruction fetch is visible on the pins only in mode 3. t iw 1.5t ns 10-8 first fetch t ra t raz t rda pab pdb reset irqa t irw
56f8323 technical data, rev. 11.0 118 freescale semiconductor preliminary figure 10-7 external level-sensitive interrupt timing figure 10-8 recovery from stop state using asynchronous interrupt timing t ig general purpose i/o pin irqa b) general purpose i/o t idm pab irqa a) first interrupt instruction execution first interrupt instruction execution not irqa interrupt vector t iw irqa t if first instruction fetch pab
serial peripheral interface (spi) timing 56f8323 technical data, rev. 11.0 freescale semiconductor 119 preliminary 10.9 serial peripheral interface (spi) timing table 10-18 spi timing 1 1. parameters listed are guaranteed by design. characteristic symbol min max unit see figure(s) cycle time master slave t c 50 50 ns ns 10-9 , 10-10 , 10-11 , 10-12 enable lead time master slave t eld 25 ns ns 10-12 enable lag time master slave t elg 100 ns ns 10-12 clock (sck) high time master slave t ch 17.6 25 ns ns 10-9 , 10-10 , 10-11 , 10-12 clock (sck) low time master slave t cl 24.1 25 ns ns 10-12 data set-up time required for inputs master slave t ds 20 0 ns ns 10-9 , 10-10 , 10-11 , 10-12 data hold time required for inputs master slave t dh 0 2 ns ns 10-9 , 10-10 , 10-11 , 10-12 access time (time to data active from high-impedance state) slave t a 4.8 15 ns 10-12 disable time (hold time to high-impedance state) slave t d 3.7 15.2 ns 10-12 data valid for outputs master slave (after enable edge) t dv 4.5 20.4 ns ns 10-9 , 10-10 , 10-11 , 10-12 data invalid master slave t di 0 0 ns ns 10-9 , 10-10 , 10-11 , 10-12 rise time master slave t r 11.5 10.0 ns ns 10-9 , 10-10 , 10-11 , 10-12 fall time master slave t f 9.7 9.0 ns ns 10-9 , 10-10 , 10-11 , 10-12
56f8323 technical data, rev. 11.0 120 freescale semiconductor preliminary 1 figure 10-9 spi master timing (cpha = 0) figure 10-10 spi master timing (cpha = 1) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14C1 lsb in t f t c t cl t cl t r t r t f t ds t dh t ch t di t dv t di (ref) t r master msb out bits 14C1 master lsb out ss (input) t ch ss is held high on master t f sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14C1 lsb in t r t c t cl t cl t f t ch t dv (ref) t dv t di (ref) t r t f master msb out bits 14C 1 master lsb out ss (input) t ch ss is held high on master t ds t dh t di t r t f
serial peripheral interface (spi) timing 56f8323 technical data, rev. 11.0 freescale semiconductor 121 preliminary figure 10-11 spi slave timing (cpha = 0) figure 10-12 spi slave timing (cpha = 1) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14C1 t c t cl t cl t f t ch t di msb in bits 14C1 lsb in ss (input) t ch t dh t r t elg t eld t f slave lsb out t d t a t ds t dv t di t r sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14C1 t c t cl t cl t ch t di msb in bits 14C1 lsb in ss (input) t ch t dh t f t r slave lsb out t d t a t eld t dv t f t r t elg t dv t ds
56f8323 technical data, rev. 11.0 122 freescale semiconductor preliminary 10.10 quad timer timing figure 10-13 timer timing 10.11 quadrature decoder timing note: the quadrature decoder is not available in the 56F8123 device. table 10-19 timer timing 1, 2 1. in the formulas listed, t = the clock cycle. for 60mhz operation, t = 16.67ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure timer input period p in 2t + 6 ns 10-13 timer input high / low period p inhl 1t + 3 ns 10-13 timer output period p out 1t - 3 ns 10-13 timer output high / low period p outhl 0.5t - 3 ns 10-13 table 10-20 quadrature decoder timing 1, 2 1. in the formulas listed, t = the clock cycle. for 60mhz operation, t=16.67ns. 2. parameters listed are guaranteed by design. characteristic symbol min max unit see figure quadrature input period p in 4t + 12 ns 10-14 quadrature input high / low period p hl 2t + 6 ns 10-14 quadrature phase period p ph 1t + 3 ns 10-14 p out p outhl p outhl p in p inhl p inhl timer inputs timer outputs
serial communication interface (sci) timing 56f8323 technical data, rev. 11.0 freescale semiconductor 123 preliminary figure 10-14 quadrature decoder timing 10.12 serial communication interface (sci) timing figure 10-15 rxd pulse width figure 10-16 txd pulse width table 10-21 sci timing 1 1. parameters listed are guaranteed by design. characteristic symbol min max unit see figure baud rate 2 2. f max is the frequency of operation of the system clock in mhz, which is 60mhz for the 56f8323 device and 40mhz for the 56F8123 device. br (f max /16) mbps rxd 3 pulse width 3. the rxd pin in sci0 is named rxd0 and the rxd pin in sci1 is named rxd1. rxd pw 0.965/br 1.04/br ns 10-15 txd 4 pulse width 4. the txd pin in sci0 is named txd0 and the txd pin in sci1 is named txd1. txd pw 0.965/br 1.04/br ns 10-16 phase b (input) p in p hl p hl phase a (input) p in p hl p hl p ph p ph p ph p ph rxd pw rxd sci receive data pin (input) txd pw txd sci receive data pin (input)
56f8323 technical data, rev. 11.0 124 freescale semiconductor preliminary 10.13 controller area network (can) timing note: the can is not available in the 56F8123 device. figure 10-17 bus wakeup detection 10.14 jtag timing table 10-22 can timing 1 1. parameters listed are guaranteed by design characteristic symbol min max unit see figure baud rate br can 1mbps bus wake-up detection t wakeup t ipbus s 10-17 table 10-23 jtag timing characteristic symbol min max unit see figure tck frequency of operation using eonce 1 1. tck frequency of operation must be less than 1/8 the processor rate. f op dc sys_clk/8 mhz 10-18 tck frequency of operation not using eonce 1 f op dc sys_clk/4 mhz 10-18 tck clock pulse width t pw 50 ns 10-18 tms, tdi data set up time t ds 5ns 10-19 tms, tdi data hold time t dh 5ns 10-19 tck low to tdo data valid t dv 30ns 10-19 tck low to tdo tri-state t ts 30ns 10-19 trst assertion time t trst 2t 2 2. t = processor clock period (nominally 1/60mhz) ns 10-20 t wakeup mscan_rx can receive data pin (input)
jtag timing 56f8323 technical data, rev. 11.0 freescale semiconductor 125 preliminary figure 10-18 test clock input timing diagram figure 10-19 test access port timing diagram figure 10-20 trst timing diagram tck (input) v m v il v m = v il + (v ih C v il )/2 t pw 1/f op t pw v m v ih input data valid output data valid output data valid t ds t dh t dv t ts t dv tck (input) tdi (input) tdo (output) tdo (output ) tdo (output) tms trst (input) t trst
56f8323 technical data, rev. 11.0 126 freescale semiconductor preliminary 10.15 analog-to-digital converter (adc) parameters table 10-24 adc parameters characteristic symbol min typ max unit input voltages v adin v refl v refh v resolution r es 12 12 bits integral non-linearity 1 inl +/- 2.4 +/- 3.2 lsb 2 differential non-linearity dnl +/- 0.7 < +1 lsb 2 monotonicity guaranteed adc internal clock f adic 0.5 5 mhz conversion range r ad v refl v refh v adc channel power-up time t adpu 5616 t aic cycles 3 adc reference circuit power-up time 4 t vref 25ms conversion time t adc 6 t aic cycles 3 sample time t ads 1 t aic cycles 3 input capacitance c adi 5pf input injection current 5 , per pin i adi 3ma input injection current, total i adit 20ma v refh current i vrefh 1.2 3ma adc a current i adca 25ma adc b current i adcb 25ma quiescent current i adcq 010 a uncalibrated gain error (ideal = 1) e gain +/- .004 +/- .01 uncalibrated offset voltage v offset +/- 26 +/- 32 mv calibrated absolute error 6 ae cal see figure 10-21 lsbs calibration factor 1 7 cf1 0.008597 calibration factor 2 7 cf2 -2.8 crosstalk between channels -60 db common mode voltage v common (v refh - v reflo ) / 2 v signal-to-noise ratio snr 64.6 db
analog-to-digital converter (adc) parameters 56f8323 technical data, rev. 11.0 freescale semiconductor 127 preliminary signal-to-noise plus distortion ratio sinad 59.1 db total harmonic distortion thd 60.6 db spurious free dynamic range sfdr 61.1 db effective number of bits 8 enob 9.6 bits 1. inl measured from v in = .1v refh to v in = .9v refh 10% to 90% input signal range 2. lsb = least significant bit 3. adc clock cycles 4. assumes each voltage reference pin is bypassed with 0.1 f ceramic capacitors to ground 5. the current that can be injected or sourced from an unselected adc signal input without impacting the performance of the adc. this allows the adc to operate in noisy industrial environments where inductive flyback is possible. 6. absolute error includes the effects of both gain error and offset error. 7. please see the 56f8300 peripheral users manual for additional information on adc calibration. 8. enob = (sinad - 1.76)/6.02 table 10-24 adc parameters (continued) characteristic symbol min typ max unit
56f8323 technical data, rev. 11.0 128 freescale semiconductor preliminary figure 10-21 adc absolute error over processing and temperature extremes before and after calibration for vdc in = 0.60v and 2.70v note: the absolute error data shown in the graphs above reflects the effects of both gain error and offset error. the data was taken on 15 parts: three each from four processing corner lots as well as three from one nominally processed lot, each at three temperatures: -40c, 27c, and 150c (giving the 45 data points shown above), for two input dc voltages: 0.60v and 2.70v. the data indicates that for the given population of parts, calibration significantly reduced (by as much as 34%) the collective variation (spread) of the absolute error of the population. it also significantly reduced (by as much as 80% when vdc in was 0.6v) the mean (average) of the absolute error and thereby brought it significantly closer to the ideal value of zero. although not guaranteed, it is believed that calibration will produce results similar to those shown above for any population of parts, including those which represent processing and temperature extremes.
equivalent circuit for adc inputs 56f8323 technical data, rev. 11.0 freescale semiconductor 129 preliminary 10.16 equivalent circuit for adc inputs figure 10-22 illustrates the adc input circuit during sample and hold. s1 and s2 are always open/closed at the same time that s3 is closed/open. when s1/s2 are closed & s3 is open, one input of the sample and hold circuit moves to (v refh -v reflo )/2, while the other charges to the analog input voltage. when the switches are flipped, the charge on c1 and c2 are averaged via s3, with the result that a single-ended analog input is switched to a differential voltage centered about (v refh -v reflo )/2. the switches switch on every cycle of the adc clock (open one-half adc clock, closed one-half adc clock). note that there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the s/h output voltage, as s1 provides isolation during the charge-sharing phase. one aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, v ref and the adc clock frequency. 1. parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. equivalent resistance for the esd isolation resistor and the channel select mux; 500 ohms 4. sampling capacitor at the sample and hold circuit. capacitor c1 is normally disconnected from the input and is only connected to it at sampling time; 1pf figure 10-22 equivalent circuit for a/d loading 10.17 power consumption see part 10 for a list of idd requirements for the 56f8323. this section provides additional detail which can be used to optimize power consumption for a given application. power consumption is given by the following equation: a, the internal [static component], is comprised of the dc bias currents for the oscillator, current, pll, and voltage references. these sources operate independently of processor state or operating frequency. b, the internal [state-dependent component], reflects the supply current required by certain on-chip resources only when those resources are in use. these include ram, flash memory and the adcs. total power = a: internal [static component] +b: internal [state-dependent component] +c: internal [dynamic component] +d: external [dynamic component] +e: external [static] 1 2 3 analog input 4 s1 s2 s3 c1 c2 s/h c1 = c2 = 1pf (v refh - v reflo )/2
56f8323 technical data, rev. 11.0 130 freescale semiconductor preliminary c, the internal [dynamic component], is classic c*v 2 *f cmos power dissipation corresponding to the 56800e core and standard cell logic. d, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading on the external pins of the chip. this is also commonly described as c*v 2 *f, although simulations on two of the io cell types used on the 56800e reveal that the power-versus-load curve does have a non-zero y-intercept. power due to capacitive loading on output pins is (first order) a function of the capacitive load and frequency at which the outputs change. table 10-25 provides coefficients for calculating power dissipated in the io cells as a function of capacitive load. in these cases: totalpower = ((intercept + slope*cload)*frequency/10mhz) where: ? summation is performed over all output pins with capacitive loads ? totalpower is expressed in mw ? cload is expressed in pf because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. e, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. sum the total of all v 2 /r or iv to arrive at the resistive load contribution to power. assume v = 0.5 for the purposes of these rough calculations. for instance, if there is a total of eight pwm outputs driving 10ma into leds, then p = 8*.5*.01 = 40mw. in previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible. table 10-25 io loading coefficients at 10mhz intercept slope 8ma cmos 3-state output pad with input-enabled pull-up 1.3 0.11mw / pf 4ma cmos 3-state output pad with input-enabled pull-up 1.15mw 0.11mw / pf
56f8323 package and pin-out information 56f8323 technical data, rev. 11.0 freescale semiconductor 131 preliminary part 11 packaging 11.1 56f8323 package and pin-out information this section contains package and pin-out information for the 56f8323. this device comes in a 64-pin low-profile quad flat pack (lqfp). figure 11-1 shows the package outline for the 64-pin lqfp, figure 11-3 shows the mechanical parameters for this package, and table 11-1 lists the pin-out for the 64-pin lqfp case. figure 11-1 top view, 56f8323 64-pin lqfp package orientation mark pin 1 17 33 49 freescale 56f8323 tc0 pwma0 pwma1 v cap 3 v dd_io pwma2 pwma3 pwma4 pwma5 v ss irqa faulta0 faulta1 faulta2 isa0 reset v dd_io extal ocr_dis v ss v cap 4 v dda_osc_pll v dda_adc v refh v ssa_adc v reflo v refp v refmid v refn temp_sense ana7 xtal tc1 can_tx can_rx v ss v dd_io trst v cap 1 tdo tdi tms tck phasea0 phaseb0 index0 home0 tc3 v ss isa2 v dd_io ss0 miso0 v cap 2 mosi0 sclk0 ana0 ana1 ana2 ana3 ana4 ana5 ana6 isa1
56f8323 technical data, rev. 11.0 132 freescale semiconductor preliminary table 11-1 56f8323 64-pin lqfp package identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1tc017v ss 33 ana7 49 home0 2 reset 18 isa1 34 temp_sense 50 index0 3 pwma0 19 isa2 35 v refn 51 phaseb0 4pwma120 v dd_io 36 v refmid 52 phasea0 5v cap 321 ss0 37 v refp 53 tck 6v dd_io 22 miso0 38 v reflo 54 tms 7pwma223 v cap 239 v ssa_adc 55 tdi 8 pwma3 24 mosi0 40 v refh 56 tdo 9 pwma4 25 sclk0 41 v dda_adc 57 v cap 1 10 pwma5 26 ana0 42 v dda_osc_pll 58 trst 11 v ss 27 ana1 43 v cap 459v dd_io 12 irqa 28 ana2 44 v ss 60 v ss 13 faulta0 29 ana3 45 ocr_dis 61 can_rx 14 faulta1 30 ana4 46 extal 62 can_tx 15 faulta2 31 ana5 47 xtal 63 tc3 16 isa0 32 ana6 48 v dd_io 64 tc1
56F8123 package and pin-out information 56f8323 technical data, rev. 11.0 freescale semiconductor 133 preliminary 11.2 56F8123 package and pin-out information this section contains package and pin-out information for the 56F8123. this device comes in a 64-pin low-profile quad flat pack (lqfp). figure 11-1 shows the package outline for the 64-pin lqfp, figure 11-3 shows the mechanical parameters for this package, and table 11-1 lists the pin-out for the 64-pin lqfp case. figure 11-2 top view, 56F8123 64-pin lqfp package orientation mark pin 1 17 33 49 freescale 56F8123 tc0 gpioa0 gpioa1 v cap 3 v dd_io ss1 miso1 mosi1 sclk1 v ss irqa gpioa6 gpioa7 gpioa8 gpioa9 reset v dd_io extal ocr_dis v ss v cap 4 v dda_osc_pll v dda_adc v refh v ssa_adc v reflo v refp v refmid v refn nc ana7 xtal tc1 gpioc3 gpioc2 v ss v dd_io trst v cap 1 tdo tdi tms tck ta0 ta1 ta2 ta3 tc3 v ss gpioa11 v dd_io ss0 miso0 v cap 2 mosi0 sclk0 ana0 ana1 ana2 ana3 ana4 ana5 ana6 gpioa10
56f8323 technical data, rev. 11.0 134 freescale semiconductor preliminary table 11-2 56F8123 64-pin lqfp package identification by pin number pin no. signal name pin no. signal name pin no. signal name pin no. signal name 1tc017v ss 33 ana7 49 ta3 2 reset 18 gpioa10 34 nc 50 ta2 3 gpioa0 19 gpioa11 35 v refn 51 ta1 4gpioa120 v dd_io 36 v refmid 52 ta0 5v cap 321 ss0 37 v refp 53 tck 6v dd_io 22 miso0 38 v reflo 54 tms 7 ss1 23 v cap 239 v ssa_adc 55 tdi 8miso124mosi040 v refh 56 tdo 9mosi125sclk041 v dda_adc 57 v cap 1 10 sclk1 26 ana0 42 v dda_osc_pll 58 trst 11 v ss 27 ana1 43 v cap 459v dd_io 12 irqa 28 ana2 44 v ss 60 v ss 13 gpioa6 29 ana3 45 ocr_dis 61 gpioc2 14 gpioa7 30 ana4 46 extal 62 gpioc3 15 gpioa8 31 ana5 47 xtal 63 tc3 16 gpioa9 32 ana6 48 v dd_io 64 tc1
56F8123 package and pin-out information 56f8323 technical data, rev. 11.0 freescale semiconductor 135 preliminary figure 11-3 64-pin lqfp mechanical information ab ab e/2 e 60x x=a, b or d c l view y s 0.05 q q q 1 ( 2) 0.25 gage plane seating plane a2 (s) r1 2x r (l1) (l2) l a1 view aa b1 section ab-ab b c1 c plating base metal rotated 90 clockwise a-b m 0.08 d c 64 0.2 ha-bd 1 49 48 17 16 32 33 b e/2 e e1 d1 d/2 d d1/2 3x view y a 4x view aa 0.08 c q ( 3) 4x 4x 4x 16 tips 0.2 ca-bd e1/2 a d c h x dim min max millimeters a --- 1.60 a1 0.05 0.15 a2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 d 12.00 bsc d1 10.00 bsc e 0.50 bsc e 12.00 bsc e1 10.00 bsc l 0.45 0.75 l1 1.00 ref l2 0.50 ref r1 0.10 0.20 s 0.20 ref q 0 7 q 0 --- q 12 ref q 12 ref notes: 1. dimensions and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane datum h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane datum c. 5. dimensions d and e to be determined at seating plane datum c. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 per side. 7. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.35. minimum space between protrusion and adjacent lead or protrusion 0.07. 1 2 3
56f8323 technical data, rev. 11.0 136 freescale semiconductor preliminary part 12 design considerations 12.1 thermal design considerations an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r j x p d ) where: the junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where: r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt x p d ) where: t a = ambient temperature for the package ( o c) r j = junction-to-ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w t t = thermocouple temperature on top of package ( o c) jt = thermal characterization parameter ( o c)/w p d = power dissipation in package (w)
electrical design considerations 56f8323 technical data, rev. 11.0 freescale semiconductor 137 preliminary the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. from this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. 12.2 electrical design considerations use the following list of considerations to assure correct operation of the 56f8323/56F8123: ? provide a low-impedance path from the board power supply to each v dd pin on the device, and from the board ground to each v ss (gnd) pin ? the minimum bypass requirement is to place six 0.01C0.1 f capacitors positioned as close as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa. ceramic and tantalum capacitors tend to provide better performance tolerances. ? ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss (gnd) pins are less than 0.5 inch per capacitor lead ? use at least a four-layer printed circuit board (pcb) with two inner layers for v dd and v ss ? bypass the v dd and v ss layers of the pcb with approximately 100 f, preferably with a high-grade capacitor such as a tantalum capacitor caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.
56f8323 technical data, rev. 11.0 138 freescale semiconductor preliminary ? because the devices output signals have fast rise and fall times, pcb trace lengths should be minimal ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and v ss circuits. ? take special care to minimize noise levels on the v ref , v dda and v ssa pins ? designs that utilize the trst pin for jtag port or eonce module functionality (such as development or debugging systems) should allow a means to assert trst whenever reset is asserted, as well as a means to assert trst independently of reset . designs that do not require debugging functionality, such as consumer products, should tie these pins together. ? because the flash memory is programmed through the jtag/eonce port, the designer should provide an interface to this port to allow in-circuit flash programming 12.3 power distribution and i/o ring implementation figure 12-1 illustrates the general power control incorporated in the 56f8323/56F8123. this chip contains two internal power regulators. one of them is powered from the v dda_osc_pll pin and cannot be turned off. this regulator controls power to the internal clock generation circuitry. the other regulator is powered from the v dd_io pins and provides power to all of the internal digital logic of the core, all peripherals and the internal memories. this regulator can be turned off, if an external v dd_core voltage is externally applied to the v cap pins. in summary, the entire chip can be supplied from a single 3.3 volt supply if the large core regulator is enabled. if the regulator is not enabled, a dual supply 3.3v/2.5v configuration can also be used. notes: ? flash, ram and internal logic are powered from the core regulator output ?v pp 1 and v pp 2 are not connected in the customer system ? all circuitry, analog and digital, shares a common v ss bus figure 12-1 power management reg core v cap i/o adc v dd v ss ocs reg v dda_osc_pll rosc v ssa_adc v dda_adc v refh v refp v refmid v refn v reflo
power distribution and i/o ring implementation 56f8323 technical data, rev. 11.0 freescale semiconductor 139 preliminary part 13 ordering information table 13-1 lists the pertinent information needed to place an order. consult a freescale semiconductor sales office or authorized distributor to determine availability and to order parts. table 13-1 ordering information part supply voltage package type pin count frequency (mhz) temperature range order number mc56f8323 3.0C3.6 v low-profile quad flat pack (lqfp) 64 60 -40 to + 105 c mc56f8323vfb60 mc56f8323 3.0C3.6 v low-profile quad flat pack (lqfp) 64 60 -40 to + 125 c mc56f8323mfb60 mc56F8123 3.0C3.6 v low-profile quad flat pack (lqfp) 64 40 -40 to + 105 c mc56F8123vfb
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